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Larger output load capacitance - PowerPoint PPT Presentation

ELEC 2200-002 Digital Logic Circuits Fall 2008 Power Dissipation

ELEC 2200-002 Digital Logic Circuits Fall 2008 Power Dissipation. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu. CMOS Logic (Inverter). VDD.

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330 views • 17 slides

Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS

Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS. Chao Han ELEC 6270. Objective. Understand the influence of frequency in power and energy saving for certain CMOS technology (180nm and 32nm)

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235 views • 11 slides

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Larger output load capacitance - PowerPoint PPT Presentation

ELEC 2200-002 Digital Logic Circuits Fall 2008 Power Dissipation

Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS