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Adaptive Cache-Line Size Management on 3D Integrated Microprocessors

Adaptive Cache-Line Size Management on 3D Integrated Microprocessors. ISOCC 2009. Takatsugu Ono, Koji Inoue and Kazuaki Murakami Kyushu University, Japan. Outline. Introduction Software Controllable-Variable Line Size (SC-VLS) Cache Evaluation Summary. 3D Integration.

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Larger cache line size - PowerPoint PPT Presentation

Adaptive Cache-Line Size Management on 3D Integrated Microprocessors