'L2 cache switch switch' presentation slideshows

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. Michael Zhang & Krste Asanovic Computer Architecture Group MIT CSAIL. Chip Multiprocessors (CMPs) are Here. Easily utilizes on-chip transistors Naturally exploits thread-level parallelism

567 views • 36 slides