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EE 447 VLSI Design Lecture 7: Combinational Circuits

EE 447 VLSI Design Lecture 7: Combinational Circuits. Outline. Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio. Example 1. module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule

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Linear Delay Model

In general the propagation delay of a gate can be written as: d = f + p p is the delay due to intrinsic capacitance. f is the effort delay or stage effort and depends on the complexity and fanout of the gate.

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Input arrival - PowerPoint PPT Presentation

EE 447 VLSI Design Lecture 7: Combinational Circuits

Linear Delay Model