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CLK

D. D. Q. Q. C. C. Figure 1. I4. X. A. I0. G1. Y. B. I1. I5. G2. G4. I2. C. G3. G5. CLK. I3. Dff timings: Tcq= 3ns, Tsu = 2 ns, Thd = 1ns. Input/Output buffer delay = 5ns, all other gates= 4ns. Figure 2b (One solution ). A * F. MSB of F. D F F. D F F. D F F. R E G.

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CLK