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Digital Phase Follower -- Deserializer in Low-Cost FPGA

Digital Phase Follower -- Deserializer in Low-Cost FPGA. Jinyuan Wu, Z. Shi. Motivation. In HEP systems, sometime many channels of serial data must be concentrated. It will be nice if the data clock is not transmitted separately. (Just transmit a single data channel).

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Digital Phase Follower -- Deserializer in Low-Cost FPGA