'Dff layout' presentation slideshows

EE 166 PROJECT SPRING 03

389 views • 28 slides

Design Goal

TEAM W3: Digital Voice Processor 525. Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5). Design Manager: Abhishek Jajoo. Design Goal. Date: 3/22/2006 Functional Blocks and Simulation.

400 views • 21 slides

A 4 bit Serial to Parallel Converter

A 4 bit Serial to Parallel Converter . Jason Baechler Benjamin Liu Forozan Amely Trang Nguyen. Introduction. Our project is to design a 4 bit serial to parallel data stream converter. Project Specification. 25Mhz Clock 50% clock duty cycle Power is less than 500 mW Vth = 2.5 V

773 views • 19 slides

4-bit Grey Code Converter with Counter

4-bit Grey Code Converter with Counter. Lincoln Chin Dat Tran Thao Nguyen Tien Huynh. Function Convert from binary to grey code Count from binary 0-15. Run with 200MHz Clock Load capacitance of 50fF Power = Area = (388 x 245)um^2 = 95060 um^2. Specifications. Design Converter

224 views • 19 slides