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HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping

HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan Brent Nelson and Brad Hutchings FCCM May 2, 2011. Design Cycle. The Problem. FPGA Compilation Times Severely Limit Turns Per Day.

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HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping