'Count myinc' presentation slideshows

module rtl_example (reset_n, clk, a, b, f, count); input reset_n; input clk;

module rtl_example (reset_n, clk, a, b, f, count); input reset_n; input clk; input [7:0] a; input [7:0] b; output [7:0] f; output [7:0] count; reg [7:0] f; // signals written to in always blocks are reg [1:0] state; // declared as reg. will synthesize to FFs

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