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Memory Management in NUMA Multicore Systems: Trapped between Cache Contention and Interconnect Overhead

Memory Management in NUMA Multicore Systems: Trapped between Cache Contention and Interconnect Overhead. Zoltan Majo and Thomas R. Gross Department of Computer Science ETH Zurich. NUMA multicores. Processor 0. Processor 1. 0. 1. 2. 3. Cache. Cache. MC. MC. MC. IC. IC. IC. IC.

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C cache cache m - PowerPoint PPT Presentation

Memory Management in NUMA Multicore Systems: Trapped between Cache Contention and Interconnect Overhead