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Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications

Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications. G. Lhairech-Lebreton , P. Coussy, D. Heller, E. Martin University Bretagne-Sud / Lab-STICC ghizlane.lhairech@univ-ubs.fr December 14, 2010. Outline. Introduction The proposed approach Experimental results

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419 views • 28 slides

Bitwidth-Aware Scheduling and Binding in High-Level Synthesis

Bitwidth-Aware Scheduling and Binding in High-Level Synthesis. X. Cheng + , J. Cong, Y. Fan, G. Han, J. Lin, J. Xu + , Z. Zhang Computer Science Department, UCLA + Microprocessor Development and Research Center, PKU. Outline. Motivation Bitwidth-aware synthesis flow

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287 views • 28 slides

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Bitwidth - PowerPoint PPT Presentation

Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications

Bitwidth-Aware Scheduling and Binding in High-Level Synthesis