'Aware timing analysis optimization' presentation slideshows

Mohit Gupta, Kwangok Jeong and Andrew B. Kahng UCSD VLSI CAD Laboratory kjeong@vlsicad.ucsd.edu

Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Double Patterning Lithography. Mohit Gupta, Kwangok Jeong and Andrew B. Kahng UCSD VLSI CAD Laboratory kjeong@vlsicad.ucsd.edu ECE Department University of California, San Diego. Outline.

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