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Bypass Aware Instruction Scheduling for Register File Power Reduction

1 CECS, ICS, UC Irvine, CA, USA. S. L. C. Bypass Aware Instruction Scheduling for Register File Power Reduction. Sanghyun Park 2 Aviral Shrivastava 1 Nikil Dutt 1 Alex Nicolau 1 Yunheung Paek 2 Eugene Earlie 3. 2 SEE, SNU Seoul, Korea. 3 SCL, Intel, Hudson, MA, USA. Processor Power.

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