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Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning

Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning. X. He, S. Dong, Y. Ma, X. Hong Tsinghua University, Beijing, China. ISQED 2009. Outline. Introduction Problem formulation Preliminary Buffer planning for 3D ICs Algorithm improvement Experiments Conclusion.

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2d buffer planning - PowerPoint PPT Presentation

Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning