Virtual Memory Management

1. Virtual Memory Management Klara Nahrstedt/Sam King October 5, 2007

2. Administrative • Midterm – October 8, Monday, 10-10:50am • 1304 SC – on-campus students • 3405 SC – local Internet students • Topics • see newsgroup for reading list • no VMM and memory management on midterm • HW1 – deadline October 5, Friday, midnight • Submission on compass, • Submission format pdf or doc • Length – as much as you need to explain the problems

3. Midterm • the midterm is closed book and you are not allowed to use any notes  • You may not have any electronics with you such as a cell phone, PDA, iPod, laptop, etc. • the midterm will be in class and you will have 50 minutes to complete it  • it contains a mix of true / false / multiple choice, programming and problem solving questions.  • for the programming questions, you may use pseudo code as long as your algorithms are clear and understandable • you are responsible for the material covered in lecture up to and including EDF scheduling • you are responsible for the material covered in the book, even if we did not discuss it in lecture  • the emphasis will be on material from lecture, but we may ask questions from the reading as well

4. Memory Management (Review) • Basic Memory Management • Mono-programming without Swapping or Paging • Multiprogramming with Fixed Partitions • Swapping • Variable Partitions • Virtual Memory Management • Paging • Page Table • Multi-level Page Tables • TLB – Translation Lookaside Buffers • Page Replacement Algorithms • Optimal • FIFO • Second Chance • LRU • Clock Page Replacement • Working Set

5. Basic Memory ManagementMonoprogramming without Swapping or Paging Three simple ways of organizing memory - an operating system with one user process

6. Multiprogramming with Fixed Partitions 0k • Divide memory into n (possible unequal) partitions. 4k 16k 64k Free Space 128k

7. Multiprogramming with Fixed Partitions • Fixed memory partitions • separate input queues for each partition • single input queue

8. Modeling Multiprogramming CPU utilization as a function of number of processes in memory Degree of multiprogramming

9. Multiprogramming Problems • What are the essential problems that must be solved when introducing multiprogramming?

10. Relocation Register Base Register Memory BA CPU Instruction Address Physical Address Logical Address + MA MA+BA

11. Protection • Problem: • How to prevent a malicious process to write or jump into other user's or OS partitions?

12. Base Bounds Registers Bounds Register Base Register Memory Base Address Logical Address LA Base Address BA CPU Address MA+BA < + Memory Address MA Physical Address PA Limit Address Fault

13. Swapping • What is swapping? • Why was swapping introduced? CS 423g - Operating Systems, Klara Nahrstedt

14. Variable Partitions and Fragmentation Free 1 Monitor Job 1 Job 2 Job 3 Job 4 2 Free Monitor Job 1 Job 3 Job 4 3 Free Monitor Job 1 Job 5 Job 3 Job 4 Free 4 Monitor Job 5 Job 3 Job 4 Job 6 Free 5 Monitor Job 7 Job 5 Job 3 Job 8 Job 6 Memory wasted by External Fragmentation CS 423g - Operating Systems, Klara Nahrstedt

15. Memory Management with Bit Maps and Lists • Part of memory with 5 processes, 3 holes • tick marks show allocation units • shaded regions are free • Corresponding bit map • Same information as a list

16. Storage Placement Strategies • Analogy: • Shoe Fitting • Valet parking • Best Fit • First Fit • Next Fit. • Worst Fit.

17. Virtual Memory The position and function of the MMU

18. Paging The relation betweenvirtual addressesand physical memory addres-ses given bypage table

19. Real Memory Request Page 3 Page Table 1 VM Frame Memory 3 1 2 2 3 3 4 4 1 2 3 4 Virtual Memory Stored on Disk Disk 1 2 3 4 5 6 7 8 Paging Request

20. Real Memory Request Page 1 Page Table 1 VM Frame Memory 3 1 2 1 2 3 3 4 4 1 2 3 4 Virtual Memory Stored on Disk Disk 1 2 3 4 5 6 7 8 Paging

21. Real Memory Request Page 6 Page Table 1 VM Frame Memory 3 1 2 1 2 3 6 3 4 4 1 2 3 4 Virtual Memory Stored on Disk Disk 1 2 3 4 5 6 7 8 Paging

22. Real Memory Request Page 2 Page Table 1 VM Frame Memory 3 1 2 1 2 3 6 3 2 4 4 1 2 3 4 Virtual Memory Stored on Disk Disk 1 2 3 4 5 6 7 8 Paging

23. Real Memory Request Page 8: Swap page 2 to disk first Page Table 1 VM Frame Memory 3 1 2 1 2 3 6 3 4 2 4 1 2 3 4 Virtual Memory Stored on Disk Disk 1 2 3 4 5 6 7 8 Paging

24. Real Memory Load Page 8 to Memory Page Table 1 VM Frame Memory 3 1 2 8 2 3 6 3 4 2 4 1 2 3 4 Virtual Memory Stored on Disk Disk 1 2 3 4 5 6 7 8 Paging

25. Page Tables Typical page table entry

26. Virtual Memory Virtual Address (P,D) P Page Table P D 0 D P 1 Contents(P,D) 0 1 P-> F 1 0 Physical Memory 1 F D F Physical Address (F,D) D Contents(F,D) Page Mapping Hardware

27. Page Mapping Hardware Virtual Memory Virtual Address (004006) 004 Page Table 004 006 0 006 4 1 Contents(4006) 0 1 4-> 5 1 0 Physical Memory 1 005 006 005 Physical Address (F,D) 006 Contents(5006)

28. Page Fault • Access a virtual page that is not mapped into any physical page • A fault is triggered by hardware • Page fault handler (by VM Software, a part of OS) • Find if there is any free physical page available • If no, evict some resident page to disk (swapping space) • Allocate a free physical page • Load the faulted virtual page to the prepared physical page • Modify the page table

29. Paging Issues • Page size is 2n • usually 512, 1k, 2k, 4k, or 8k • E.g. 32 bit VM address may have 220 (1MB) pages with 4k (212 ) bytes per page • Page table: • 220 page entries take 222 bytes (4MB) • page frames must map into real memory • Page Table base register must be changed for context switch • What kind of fragmentation does paging experience?

30. Virtual-To-Physical Lookups • Programs only know virtual addresses • The page table can be extremely large • Each virtual address must be translated • Page table stored in memory • So, each program memory access requires several actual memory accesses • Solution: cache “active” part of page table • TLB also called “associative memory”

31. Translation Look-aside Buffer (TLB) VPage # Virtual address offset VPage# PPage# ... Real page table Miss VPage# PPage# ... . . . VPage# PPage# ... TLB Hit PPage # offset Physical address

32. TLBs – Translation Lookaside Buffers A TLB to speed up paging

33. Paging Implementation Issues • TLB can be implemented using • Associative registers • Look-aside memory • Content-addressable memory • TLB hit ratio (Page address cache hit ratio) • Percentage of time page found in associative memory

34. Group Discussion • Similarity between Cache and TLB • Difference between Cache and TLB

35. Issues • What TLB entry to be replaced? • Random • Pseudo Least Recently Used (LRU) • What happens on a context switch? • Process tag: change TLB registers and process register • No process tag: Invalidate the entire TLB contents • What happens when changing a page table entry? • Change the entry in memory • Invalidate the TLB entry

36. Effective Access Time • TLB lookup time =  time unit • Memory cycle -- m microsecond • TLB Hit ratio --  • Effective access time • Eat = (1m+)(2m+)(1-) • Eat = 2m+-

37. Multilevel Page Tables • Since the page table can be very large, one solution is to page the page table • Divide the page number into • An index into a page table of second level page tables • A page within a second level page table • What is the advantage to have multilevel page tables?

38. Page Tables Second-level page tables • 32 bit address with 2 page table fields • Two-level page tables Top-level page table

39. Example Addressing on a Multilevel Page Table System • A logical address (on 32 bit machine with 4k page size) is divided into • A page number consisting of 20 bits • A page offset consisting of 12 bits • Divide the page number into • A 10-bit page number • A 10-bit page offset • Problem: • Assume 32 bit machine with 8K page size? What would be P1 and P2 and D?

40. Conclusion • Paging Concept in VM • VM Issues • Address Translation • Multilevel paging • Fragmentation • Page Sizes • Page Replacements