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Design and Implementation of Softcore Dual Processor System on Single Chip FPGA

This project involves designing and implementing a softcore dual processor system on a single Field Programmable Gate Array (FPGA) chip. The system includes communication processors, computing processors, and a time-to-digital converter for statistical computation, all integrated using SoC principles. The hardware overview includes details of the FPGA device used and software components such as TCP/IP stack implementation and real-time operating system for embedded devices. Resource sharing, dual processor system design, and communication protocols are critical aspects of this project. The FPGA resource utilization is optimized with small resource usage and efficient computing power allocation. The system allows for measurement control via Internet connection and display of measurement results. Thank you for your attention.

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Design and Implementation of Softcore Dual Processor System on Single Chip FPGA

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  1. Military University of Technology Faculty of Electronics Institute of Telecommunication Design and implementation of softcore dual processor system on single chip FPGA Maciej Gołaszewski Tutor: Tadeusz Sondej, PhD

  2. Multiprocessor SoCs in FPGA Softcore processor – Processor core available as IP-Core. Described in Hardware Description Language (HDL) like VHDL or Verilog. SoC – integration of main system elements like microprocessor, timers, registers,memory controllers or communication modules in programmable device (FPGA) registers FPGA – Field Programmable Gate Array Examples:NIOS II from Altera,MicroBlaze form Xilinx

  3. Processor communication Shared memory (SM) • all processors have common address space • processors can have own local memory (M) • to communicate processors modify data in shared memory Message passing • processors have separate address space • communication is realized by sending messages • processors are directly connected

  4. Resource sharing • only one of the processors should use the shared resource at the same time • to restrict access to shared resource should be used a semaphore • Shared memory should be accessed only after successful acquiring of the semaphore

  5. Dual processor system design System tasks: • control the time-to-digital converterin FPGA • Statistical computation during time intervals measurements • Measurement control via Internet connection communication processor computing processor

  6. Time-to-digital converter • 32 binary counters counting periods of 16-phase clockof the 400 MHz frequency (both edges of clock are active) • equivalent of a single clock signal of 12.8 GHz frequency • provides 78 ps resolution in a single stage interpolation • measurement range 164 μs can be easily extended

  7. System hardware overview communication processor computing processor FPGA device: Stratix II EP2S60 (Altera)

  8. Hardware implementation Nios II Developement Kit Stratix II Edition JTAG Ethernet UART Flash 16MB SSRAM 2MB DDR SDRAM32MB LEDs prototype connectors Push buttons FPGA device: Stratix II EP2S60 (Altera)

  9. Software • TCP/IP stack implemantationfrom InterNiche – NicheStack • Real-time operating system (RTOS) for embedded devices – µC/OS-II • Multithreaded application • Code optimized for statistical computation • Time-to-digital converter software drivers • Single threaded application

  10. Host PC application • Programming language: JAVA • Measurement control via Internet connection. • Measurement result display. • Measurement series histogram presentation.

  11. Conclusion FPGA resource utilization • Small resource utilization – 13% of Stratix II EPS2S60. • System clock – 100 MHz • Computing power of one processor is reservedonly for statistical computation. • Measurement control via Internet connection.

  12. Thank you for your attention Maciej Gołaszewski

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