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Background for Leakage Current. Sept. 18, 2006. Active power density increasing with device scaling and increased frequency Leakage power density increasing due to lower V t and gate leakage Stressing packaging, cooling, battery life, etc. Complicates IDDq testing as well.

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slide2

Active power density increasing with

device scaling and increased frequency

  • Leakage power density increasing due

to lower Vt and gate leakage

  • Stressing packaging, cooling, battery

life, etc.

  • Complicates IDDq testing as well

Thinning gate oxides increase

gate tunneling leakage

Power Challenge

Source from Bergamaschi

problem statement
Problem Statement
  • Power Analysis on CMOS Inverter
problem statement4
Problem Statement
  • Dynamic Power
  • Average Short Circuit Current
  • Sub-threshold Leakage Current
problem statement5

Feature Size

> 0.25um

0.18/0.13/0.09um…

Performance(AP)

< 200MHz

300/400/533MHz, 1GHz

Core Voltage

5.0/3.3/2.5V

1.8/1.2/1.0V …

VTH(Threshold)

> +/- 0.6V

+/- 0.5, 0.4, 0.3V …

TR Leakage

Negligible

Exponential growing(SD/Gate)

Stand-by Mode

PLL-off(Clock-off)

V/MTMOS, High VTH/High VDD

Low Power

Focus on Operating Power

Focus on Operating/Stand-by

Problem Statement
  • Domination of Leakage Current
active and leakage power with cmos scaling
As CMOS scales down the following stand-by leakage current rises rapidly.

Source to drain leakage (diffusion+tunneling) as Lg scales down

Gate leakage current (tunneling) as Tox scales down

Body to drain leakage current (tunneling) as channel doping scales up

Active and Leakage Power with CMOS Scaling
two cases of leakage mechanism

Vg=0V

Sub-threshold Leakage

Turn off

Source to drain tunneling

Gate oxide tunneling

Vd=Vdd

Drain to Body tunneling (BTB)

Vg=Vdd

Turn on

Vd=0V

Two cases of Leakage Mechanism
gate leakage current reduction with high k gate dielectric

)

1

10

2

0

10

-1

10

Drain leakage

-2

10

High-K gate dielectric

Current Density (A/cm

-3

10

Gate leakage

-4

10

-5

10

-6

10

20

25

30

35

40

Tox (A)

Gate Leakage Current Reduction with High-K Gate Dielectric
slide9
Voltage Scaling for Low Power

Low Power

P VDD2

Low VDD

I ds  (VDD- Vth)1~2

Low Speed

Speed Up

I ds  (VDD -Vth)1~2

Low Vth

I leakage  e-C xVth

High Leakage

Leakage Suppression

low leakage solution technology

100m

VTH control

VDD control

MTCMOS

High speed

High speed

10m

VDD: 1.5V

VDD control

Dynamic power[W]

VDD: 1.0V

1m

VTH control

Low speed

Low speed

VTH: 0.5V

VTH: 0.25V

100n

1p

10p

100p

1n

10n

100n

Leakage power[W]

Low-Leakage Solution – Technology
vtcmos mtcmos

Multi-Threshold CMOS

Variable-Threshold CMOS

Schematic Diagram

VDD

Vpb

= VDD

N-well

VDD

or V+

Low-

Vth

Vt

Low

Vt

Control

circuit

Sleep

Hi-

Vth

GND

P-well

Vnb

= 0 or V-

GND

principle

  • On-off control of internal VDD or VSS
  • Special F/Fs, Two Vth’s
  • Threshold control with bulk-bias
  • Triple well is desirable

Merit

  • Low leakage in stand-by mode.
  • Conventional design Env.
  • Low leakage in stand-by mode.
  • Conventional design Env.

Demerit

  • Large serial MOSFET
    • ground bounce noise
  • Ultra-low voltage region?(1V)
  • Scalability? (junction leakage)
  • TR reliability under 0.1mm
    • Latch-up immunity, Vth controllability, Substrate noise, Gate oxide reliability
  • Gate leakage current
VTCMOS & MTCMOS
mtcmos reduce stand by power with high speed
MTCMOS : Reduce Stand-by Power with High Speed

With High VTH switch (MTCMOS)

Without High VTH switch

Vdd

  • With High VTH switch, much lower leakage current flows between Vdd and Vss
  • High VTH MOSFET should have much lower ( >10X) leakage current compared to normal VTH MOSFET

Vdd

Normal or Low VTH MOSFET

0

1

0

1

Virtual Ground

Vss

0

Vss

High VTH switch

multi threshold cmos mtcmos

Active

Sleep

Active

Multi-Threshold CMOS (MTCMOS)
  • Mobile Applications
    • Mostly in the idle state
    • Sub-threshold leakage Current
  • Power Gating
    • Low VTH Transistors for High Performance Logic Gates
    • High VTH Transistors for Low Leakage Current Gates

Current

Cutoff-Switch

(High Vth)

Logic Component (Low Vth)

VDD

Operating

Mode

Low Vth

MOS

Sleep Control (SC)

SC

High Vth

MOS

VGND

VSS

Time

ccs sizing

High

Vt

CCS Sizing
  • The effect of CCS size
    • As the size decreases, logic performance also decreases.
    • As the size increases, leakage current and chip area also increase.
    • Proper sizing is very important.
    • CCS size should be decided within 2% performance degradation.

VDD

Low Vt

Vop = VDD - V

Switch

Vmust be sizedwithin 2% performance degradation.

Control

GND

itrs roadmap
ITRS roadmap
  • Scaling down allows the same performance with reduced voltage, leading to low power.
  • From 0.18 micron down, building a transistor with a good active current(Ion) and a low leakage current (Ioff) is difficult.
    • high-speed TR’s ; low channel doping
    • low-leakage TR’s ; high channel doping
  • Now three groups of TR’s;
    • High Performance (HP) ; high active current ; Thin Tox
    • Low Operating Power (LOP) ; low active current ; High Tox
    • Low Standby Power (LSTP) ; low static current ; High Tox
bulk cmos vs soi
Bulk CMOS vs. SOI
  • Buried oxide layer below active silicon layer -> electrical isolation of TR’s
    • Lower parasitic cap.
  • PD(Partially Depleted)
    • Floating body effect increases speed
      • Low threshold in dynamic mode
  • or FD(Fully Depl)
    • Ideal subthresold swing of 60 mV/decade
reducing subthreshold current in bulk cmos
Reducing Subthreshold current in Bulk CMOS
  • VTCMOS (Variable Threshold)
    • Tune substrate bias to adjust Vth
    • Requires efficient DC-DC converter
    • For a given technology, there an optimum in VR , as decreasing subthreshold leakage is accompanied by an increase in drain junction leakage
  • When both High Vt and Low Vt TR’s are available,
    • MTCMOS (Multi-Threshold) ; Introduce high Vt power switch to limit leakage in stby mode
    • Use low Vt for critical path
    • This can be coupled with multiple VDD’s
  • Other tricks
    • Set up the logical internal states where the total leakage is minimal.
five types of off currents
Five types of off-currents
  • Tunneling through gate oxide
    • Fowler-Nordheim tunneling -> direct tunneling
  • Subthreshold current
  • Gate-induced drain leakage (GIDL)
    • Thermal emission
    • Trap-assisted tunneling
    • BTBT
  • Reverse-biased pn junction current
    • -> band-to-band tunneling (BTBT) current
  • Bulk punch-through
gate induced drain leakage gidl
Gate-induced drain leakage (GIDL)
  • Gate-induced drain leakage (GIDL)
    • Thermal emission
    • Trap-assisted tunneling
    • BTBT
  • Fig 3.12
leakage current due to qm tunneling
Leakage current due to QM Tunneling
  • substrate and drain ; band-to-band tunneling ;
    • increases with E-field and dopant concentration due to scaling
  • source and drain ;
    • Surface punchthru due to DIBL
    • Punch-through at bulk
  • gate oxide ;
    • SiO2 has been used as it has so low trap and fixed charge density at the interface
    • Gate current is an exponential function of Tox and Vox
    • Hole tunneling is 10% of that of electron due to higher barrier height and heavier effective mass
gate leakage current reduction with high k gate dielectric23
Gate Leakage Current Reduction with High-K Gate Dielectric
  • As Tox scales gate leakage current increases exponentially due to exponential increase of tunneling probability with reduction of physical tunneling distance.
  • Physically thicker gate dielectric allows lower leakage current but lower oxide capacitance reducing on-current
  • Using high k (dielectric constant) material, both thicker physical thickness and higher oxide capacitance can be achieved.
  • Applying high-k gate dielectric, several orders of magnitude lower gate leakage current can be achieved with similar oxide capacitance
approach 1 to reduce gate leakage high k materials
Approach 1 to reduce gate leakage ; High K materials
  • To suppress gate tunneling current, use materials with
    • High K -> increases thickness (t)
    • Higher barrier height (h)
  • Using high K
    • Increases short-channel effects due to thicker gate dielectric (This sets an upper limit on K, lower limit coming from I tunnel)
    • Mobility degradation due to poor interface quality
approach 2 to reduce gate leakage stop scaling the thickness of gate oxide
Approach 2 to reduce gate leakage ; stop scaling the thickness of gate oxide
  • Thicker gate oxide yields less control of gate on channel conduction, i.e., higher short-channel effects and DIBL effects.
approach 3 to reduce gate leakage
Approach 3 to reduce gate leakage
  • Multiple gates allows better cotrol of channel by gate, and lets scaling continue without excessive short-channel effects
    • Double gate
    • FinFET
    • Triple gate
    • Quadruple or gate all-around