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Lecture 5 EGRE 254

Lecture 5 EGRE 254. 1/28/09. Boolean algebra. a.k.a. “switching algebra” deals with Boolean values -- 0, 1 Positive-logic convention analog voltages LOW, HIGH --> 0, 1 Negative logic -- seldom used Signal values denoted by variables (X, Y, FRED, etc.). Boolean operators.

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Lecture 5 EGRE 254

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  1. Lecture 5EGRE 254 1/28/09

  2. Boolean algebra • a.k.a. “switching algebra” • deals with Boolean values -- 0, 1 • Positive-logic convention • analog voltages LOW, HIGH --> 0, 1 • Negative logic -- seldom used • Signal values denoted by variables(X, Y, FRED, etc.)

  3. Boolean operators • Complement: X¢ or (opposite of X) • AND: X × Y • OR: X + Y binary operators, describedfunctionally by truth table.

  4. More definitions • Literal: a variable or its complement • X, X¢, FRED¢, CS_L • Expression: literals combined by AND, OR, parentheses, complementation • X+Y • P × Q × R • A + B × C • ((FRED × Z¢) + CS_L × A × B¢× C + Q5) × RESET¢ • Equation: Variable = expression • P = ((FRED × Z¢) + CS_L × A × B¢× C + Q5) × RESET¢

  5. Logic symbols

  6. Basic Axioms

  7. Proving theorems • Using axioms or theorems already proven. • Perfect induction – Verify theorem for all possible values of the variables. • 1 variable 2 = 21 possible values. 0, 1 • 2 variables 4 = 22 possible values. 00, 01, 10, 11 • 3 variables 8 = 23 possible values. 000, 001, …, 111 • n variables 2n possible values. • For general case of n variable we use the mathematical technique of finite induction.

  8. T1 : X + 0 = X Proof 1a If X = 0 then X + 0 = X by A4’ If X = 1 then X + 0 = X by A5’ Proof 2a,b T1’: X1 = X Proof 1b If X = 1 then X1= X by A4 If X = 0 then X1= X by A5 Proof 3b T1’ follows from duality of T1. Prove T1 and T1’

  9. Basic Theorems

  10. Theorems

  11. T8’ • Not what we would expect! • Proof 1: using truth table (perfect induction)

  12. T8’ • Proof 2: Algebraically using proved theorems (X + Y)(X + Z) = (X+Y)X +(X+Y)Z ;Why? = XX+YX+XZ+YZ ; T6’, T8 = X+XY+XZ+YZ ; T3’, T6’ = X1 + X(Y+Z) + YZ ; T1’, T8 = X(1+(Y+Z)) + YZ ; T8 = X1 + YZ ; T6, T1’ = X + YZ ; T1’ • Better (X + Y)(X + Z) = X + XZ + XY + YZ = X(1+Z+Y) + YZ = X + YZ • Proof 3: Follows from T8 and duality.

  13. Algebraic Proofs • T10: XY+XY’ = X(Y+Y’) = X1 = X • T10’: (X+Y)(X+Y’) = X+XY+XY’+YY’ = X(1+Y+Y’) + 0 = X(1) = X • T11: XY+X’Z+YZ = XY+X’Z+(XYZ+X’YZ) = XY(1+Z) + X’Z(1+Z) = XY + X’Z • T11’: Do as an exercise.

  14. Example using T9 • (A+B)’C + (A+B)’CD’(E+F) = (A+B)’C • Treat (A+B)’C as X, treat D’(E+F) as Y • Or instead of using T9 recognize that (A+B)’C + (A+B)’CD’(E+F) = (A+B)’C(1+D’(E+F)) = (A+B)’C • It is not necessary to memorize all of these theorems. • Know through T5’ and couple that with your knowledge of ordinary algebra.

  15. XOR • X  Y = XY’ + X’Y • X  0 = X • X  1 = X’ • X  X = 0 • X  X’ = 1 • X  Y  Z = X  (Y  Z) = Z  X Y

  16. How are these XOR gates used?

  17. DeMorgan’s Theorem • These are the equations you must memorize • But notice that given one it is trivial to obtain the others.

  18. Prove Alternative proof. Let X = 0 then 1Y’ = (0 + Y)’ Let X = 1, then 0Y’ = (1+Y)’ = 1’ = 0

  19. DeMorgans Theorem in n variables

  20. Generalizations • DeMorgan’s Theorem • Duality. If then

  21. Shannon’s expansion theorem Proof: Consider f(xi) = xi’f(0)xi + xif(1)xi When xi = 0 then f(0)xi = 1f(0)xi + 0f(1)xi = f(0)xi When xi = 1 then f(1)xi = 0f(0)xi + 1f(1)xi = f(1)xi Thus, by perfect induction f(xi) = xi’f(0)xi + xif(1)xi

  22. Implementation example • Draw circuit directly from equations. • Draw circuit using only NAND gates.

  23. Design example • Design a 3-input majority circuit

  24. Design example • Design a 3-input majority circuit

  25. Design example • Design a 3-input majority circuit

  26. Design example • Design a 3-input majority circuit

  27. Design example • Design a 3-input majority circuit

  28. Example • Show how to build an 8 input and gate using several two input and gates. • Which is better? Why?

  29. Schmitt-trigger gates contain input hysteresis. Useful for interfacing to slow or noisy signals.

  30. Tri-state buffers

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