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## INTRODUCTION TO LOW-POWER DESIGN

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**Why Low-Power Devices?**• Practical reasons (Reducing power requirements of high throughput portable applications) • Financial reasons (Reducing packaging costs and achieving memory savings) • Technological reasons (Excessive heat prevents the realization of high density chips and limits their functionalities)**Application Fields**• Portable Electronics (PC, PDA, Wireless) • IC Cost (Packaging and Cooling) • Reliability (Electromigration, Latch-up) • Signal Integrity (Switching Noise, DC Voltage Drop) • Thermal Design • Ultra-low-power applications • Space missions (miniaturized satellites)**Different Constraints for Different Application Fields**• Portable devices: Battery life-time • Telecom and military: Reliability (reduced power decreases electromigration, hence increases reliability) • High volume products: Unit cost (reduced power decreases packaging cost)**Driving Forces for Low-Power: Portable Applications**• The market of portable applications is growing rapidly. Global Market for Cellular Phones**Driving Forces for Low-Power: Deep-Submicron Technology**• ADVANTAGES • Smaller geometries • Higher clock frequencies • DISADVANTAGES • Higher power consumption • Lower reliability**Driving Forces for Low-Power:Battery Limitations**• Battery maximum power and capacity increases 10%-15% per year • Increasing gap with respect to power demand**What has worked up to now?**• Voltage and process scaling • Design methodologies • Power-aware design flows and tools, trade area forlower power • Architecture Design • Power down techniques • Clock gating, dynamic power management • Dynamic voltage scaling based on workload • Power conscious RT/ logic synthesis • Better cell library design and resizing methods • Cap. reduction, threshold control, transistor layout**Peak power**P(t) RMS power Average power Energy t Power Metrics • Average power: Related to battery lifetime. • Peak power: Related to reliability and thermal failure • RMS power: Related to cycle-by-cycle power • Energy=power time: Related to power-delay product.**Why CMOS?**VDD • Intrinsically low power consuming (when the input is static, there is no power consumption) • Reference technology • Ease of design. PMOS Vin Vout NMOS Basic CMOS configuration VSS**An NMOS gate**Polysilicon or Metal Oxide Gate Source Drain p n n**A biased NMOS gate**VGS>0 + + + + + + + + p n n**A biased NMOS gate**VGS>0 + + + + + + + + p n n**A parallel plate capacitance**A biased NMOS gate VGS=VTn + + + + + + + + p n n When VGS VTn , the n-channel is developed and the device can start operation by applying a positive VDS**Power Dissipation in CMOS Circuits**Ptotal = Pswitching + Pshort-circuit + Pleakage Due to charging and discharging capacitors (dynamic power consumption) Due to direct paths Due to leaking diodes and transistors %75 %20 %5**CDD** CGND Inverter: A Basic CMOS Gate**Energy Consumed (related to Battery Power)**Energy consumed due to a complete cycle 010.**Dynamic Power Consumption(related to Battery Power)**• Average power consumption by a node cycling at each period T: (each period has a 01 or a 1 0 transition) • Average power consumed by a node with partial activity • (only a fraction of the periods has a transition)**Dynamic Power Consumption(related to Inverter)**• Average power consumption by a node cycling at each period T: (each period has a 01 or a 1 0 transition) • Average power consumed by a node with partial activity • (only a fraction of the periods has a transition)**CL = Ceff**Dynamic Power Consumption • Define effective capacitance Ceff: • To minimize switching power • Reduce VDD • Reduce Ceff**Factors Influencing Ceff**• Circuit function • Circuit technology • Input probabilities • Circuit topology**Some Basic Definitions**• Signal probability of a signal g(t) is given by • Signal activity of a logic signal g(t) is given by where ng(t) is the number of transitions of g(t) in the time interval between –T/2 and T/2.**Factors Influencing Ceff:Circuit Function**• Assume that there are M mutually independent signals g1, g2,...gM each having a signal probability Pi and a signal activity Ai, for i n. • For static CMOS, the signal probability at the output of a gate is determined according to the probability of 1s (or 0s) in the logic description of the gate P1 P1 P1P2 1-(1-P1)(1-P2) P1 1-P1 P2 P2**Factors Influencing Ceff:Circuit Function (Static CMOS)**• Transistors connected to the same input are turning on and off simultaneously when the input changes • CLof a static CMOS gate is charged to VDD any time a 01 transition at the output node is required. • CL of a static CMOS gate is discharged to ground any time a 1 0 transition at the output node is required. NOR Gate**A**Y B Factors Influencing Ceff:Circuit Function (Static CMOS) • Two-input NOR gate • Assume only one input transition per cycle is allowed • Assume inputs are equiprobable: pA=pB=1/2. • The probability for the output to be 1 is pY=(1-pA)(1-pB)=1/4 • The probability for the output to be 0 is pY’=1-pY=3/4**Factors Influencing Ceff:Circuit Function (Static CMOS)**• State transition diagram of the NOR gate**A**Y B Factors Influencing Ceff:Circuit Function (Static CMOS) • Two-input XOR gate • Assume only one input transition per cycle is allowed • Assume inputs are equiprobable: pA=pB=1/2. • The probability for the output to be 1 is pY=(1-pA)pB+(1-pB)pA=1/2 • The probability for the output to be 0 is pY’=1-pY=1/2**Factors Influencing Ceff:Circuit Function (Static CMOS)**• State transition diagram of the NOR gate**f**Factors Influencing Ceff:Circuit Function (Dynamic CMOS) • At each cycle, MD is precharged to VDD. • CL is precharged to VDD at each clock cycle • It is discharged to ground any time a 1 0 transition at the output node is required. MD**A**Y B Factors Influencing Ceff:Circuit Function (Dynamic CMOS) • Two-input NOR gate • Assume only one input transition per cycle is allowed • Assume inputs are equiprobable: pA=pB=1/2. • The probability for the output to be discharged is pY’=3/4 • The probability of CL to be re-charged at the next cycle is pY’.**Factors Influencing Ceff:Circuit Function (Dynamicvs Static)**• dynamic CMOS static CMOS: • Ceff (dynamic CMOS) Ceff (static CMOS) • Power due to glitching is much smaller in dynamic CMOS than it is in static CMOS. • In static CMOS, the transition probability depends on both input probabilities and previous state. • In dynamic CMOS, the transition probability depends on solely input probabilities. • In static CMOS, the gate output does not switch if the inputs do not change between subsequent cycles. • In dynamic CMOS, the gate output may switch even if the inputs do not change between subsequent cycles.**A**Y B Factors Influencing Ceff:Input Probabilities (Static CMOS) • Two-input NOR gate • Assume only one input transition per cycle is allowed • Assume inputs are not equiprobable: pA, pB • The probability for the output to be 1 is pY=(1-pA)(1-pB) • The probability for the output to be 0 is pY’=1-pY**Factors Influencing Ceff:Input Probabilities (Static CMOS)**• The probability for the output of a NOR gate to have a 01 transition:**Factors Influencing Ceff:Input Probabilities (Static CMOS)**• Signal probability calculation: • For each input signal and gate output in the circuit, assign a unique variable • Starting from at the inputs and proceeding to the outputs, write the expression for the output of each gate as a function of its input expression • Suppress all exponents in a given expression to obtain the correct probability for that signal (Recall that an exponent of a binary number is also a binary number)**Factors Influencing Ceff:Input Probabilities (Static CMOS)**• Signal activity calculation: Boolean Difference • It signifies the condition under which output f is sensitized to input xi • If the primary inputs to function f are not spatially correlated, the signal activity at f is**Factors Influencing Ceff:Input Probabilities (Static CMOS)**• Signal activity through basic gates P1 , A1 P2 A1 + P1 A2 P1 , A A P2 , A2 P1 , A1 (1-P2 ) A1 + (1-P1) A2 P2 , A2 • Signal activity is used to determine dynamic power due to glitches.**Factors Influencing Ceff:Circuit Topology**• Circuit topology may have high impact on Ceff • Example: Chain and Tree implementation of a four input NAND gate • Assume static CMOS • Assume all inputs are equiprobable.**Factors Influencing Ceff:Circuit Topology**• Globally chain implementation has a lower switching activity in the static behavior of the circuit. • Timing skew between signals may cause hazards resulting in extra power dissipation. • Consider 11101011 in chain circuit with unit delay of each gate.**Factors Influencing Ceff:Circuit Topology**• The chain circuit suffers from hazards, but the tree circuit does not (due to its balanced paths) • Dynamic CMOS is glitch-free because the gate output can make at most one power consuming transition per clock cycle.