Update on the Design Implementation Methodology for the 130nm process (Reader ’ s digest version)

1. Update on the Design Implementation Methodology for the 130nm process (Reader’s digest version) Slides extracted from : Microelectronics User Group meeting TWEPP 2010 – Aachen Courtesy from : Sandro Bonacini CERN PH/ESE sandro.bonacini@cern.ch Kostas Kouklinas CERN PH/ESE kostas.kouklinas@cern.ch

2. Statements Implementation of digital blocks for small (~200 kgate) logic cores for digital or mixed signal ASICs Using the IBM 130 nm standard cell library Separate substrate/ground and n-well/VDD biasing for mixed signal designs Defined methodology compatible with mixed signal design flows Open Access based Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

3. Design flow components • Tools • Virtuoso 6.1.3 (OA based) • SOC Encounter 8.1 (velocity) • Conformal 8.1 • EXT 8.1.4 (QRC) • Assura 3.2 • Calibre 2009.3 • Design Kits • IBM CMOS8RF DM design kit V1.7 • 3 thin, 2 thick, 3 RF metals. • IBM CMOS8RF LM design kit V1.7 • 6 thin, 2 thick metals. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

4. CMOS8RF Mixed Signal design kit PDK Standard cell libraries • Mixed Signal Kit V1.7 • Based on foundry PDK V1.7.0.2 • Ready for release (Sept. 2010) • Foundry Standard cell and IO pad libraries • Physical Layout views available. • Access to standard cell libraries is legally covered by standing CDAs with the foundry. • New versions of CAE Tools • Compatible with the “Europractice” 2010 distribution. • Open Access database. • Bug fixes and Important updates. • Presentation by Sandro Bonacini • Support for LINUX Platform • Qualified on RHEL4 & RHEL5 CAE Tools Mixed Signal Design Kit • Two design kits available: • CMOS8RF-DM (3-2-3 BEOL) • CMOS8RF-LM (6-2 BEOL) Kostas.Kloukinas@cern.ch

5. CMOS8RF Mixed Signal Workflows • Analog & Mixed Signal (AMS) Workflows. • Formalize the design work by employingstandardized and validated Design Workflows. • Formalize the design workacross design teams in common projects. • Provide a repository with reference design examples,presented in AMS Workshop training sessions. • Development work subcontracted to Cadence,VCAD design services. • Close collaboration of CERN - VCAD - IBM • VCAD brought in their invaluable expertise on the CAE tools • IBM provided the physical IP blocks and important technical assistance • CERN assisted the development and validated the design kit functionality. • Key Technology • Design kit that supports CAE tools based on Open Access database. Kostas.Kloukinas@cern.ch

6. Recent Enhancements Digital library I/O pads Created missing views Functional and symbol views for simulation Fixed existing views Pin mismatches of power pads Abstract power pin width DRC fixes on layouts Created 45 degree corner cells Standard cells Created fillers with PC shapes Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

7. Recent Enhancements Implementation flow Added support for multiple power domain Analog, digital, … Support for P&R of mixed signal ASICs and third-party IP blocks Better integration between Virtuoso and Encounter Automatic final netlist import into Virtuoso Automated physical verification DRC and LVS Other small fixes Scan chain reordering Antenna rule definition for Encounter Two-steps routing for DM metal stack to avoid antenna 1st pass on 3 metals (only thin) 2nd pass on 5 metals (thin+thick) New double vias for denser routing / better yield Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

9. Synthesis • Timing constraints: • Clock definitions • Input delays, fanout, transition, etc. • Output load, etc. Timing constraints [.sdc] RTL description [.v] / [.vhd] Synthesis,mapping andtiming reports Max timing Liberty libraries [.lib] RTL synthesis Capacitance tables [.CapTbl] Abstract layout Definition [.lef] Mapped netlist [.v] Conformal script [.lec] RTL compiler script [.tcl] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

10. Resume Future plans Add signal integrity checks Celtic Implementation of digital blocks Using the IBM 130 nm standard cell library Defined methodology compatible with mixed signal design flows Presented in the AMS courses Open Access based Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

11. Spares Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

12. RTL Compiler [rc] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

13. Logical Equivalence Checking

14. Logic Equivalence Checking Tool: Conformal Mapped netlist [.v] RTL description [.v] / [.vhd] Conformal script [.lec] Logical Equivalence Checking Max timing Liberty libraries [.lib] LECreport Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

15. Synthesized netlist User RTL code Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

16. Floorplanning & power routing

17. Design import and floorplanning RTL description [.v] / [.vhd] Mapped netlist [.v] Min/Max timing Liberty libraries [.lib] Reports Floorplanning & power routing Capacitance tables [.CapTbl] QX tech file [.tch] • Tool: Encounter Open Access Floorplanned Design [.oa] Open Access Standard cells library [.oa] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

18. Design import DAC SRAM Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

19. Floorplanning & power routing Define Chip/core size target area utilization I/O placement module placement in case of TMR or other special constraints Power planning/routing Core/block rings and stripes DAC SRAM Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

20. Placement

21. Placement Encounter command file Open Access Floorplanned Design [.oa] Connect cells power/ground Add tap cells Placement Scan-chain reorder Reports Open Access Placed Design [.oa] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

22. Placement Power/ground connections Standard cells Scan-chain reordering Tap cells

23. Congestion analysis

24. Congestion analysis Use Encounter Trialroute to estimate congested areas Manually add placement partial blockage Change position of I/Os or blocks …or increase number of routing metals Open Access Placed Design [.oa] Congestion analysis Placement optimization Open Access Placed Design [.oa] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

25. Multiple power domains • Analog & digital blocks • Separate power supply • Breaker peripheral pads SRAM DAC

26. Timing optimization Clock tree synthesis Timing optimization Routing Timing optimization

27. Automatic P&R steps Open Access Placed Design [.oa] Timing optimization Clock tree synthesis Timing optimization Routing Timing optimization Open Access Routed Design [.oa] Reports Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

28. Clock tree synthesis & signal routing Clock tree synthesis Routing onthin metals Routing on all metals Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

29. DFM Signoff RC extraction Timing analysis

30. Design for manufacturing Open Access Routed Design [.oa] Antenna fix Final netlist [.v] Via optimization Cells & metal fill Open Access Final Design [.oa] Signoff RC extraction Delay file [.sdf] Signal integrity analysis Signoff timingreport Timing analysis Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

31. Antenna fix Re-routes long nets Inserts tie-down diodes Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

32. Via optimization Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

33. Cells & metal fill Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

34. Timing closure If signoff timing analysis reports violations increase buffer sizes add extra buffers reroute signals check constraints exploit useful skew annotate native post-route RC extraction tool re-run optimization Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

35. Logical Equivalence Checking DRC LVS

36. Virtuoso OA design is present in Virtuoso Easily included in a mixed-signal chip SRAM DAC Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

37. Calibre DRC – Assura LVS