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Trigger System

Trigger System

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Trigger System

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  1. Trigger System LIU Zhen’an Inst. of High Energy Physics, Beijing Sep. 17 2002

  2. Outline • General • Event Rate • design rules • trigger in data flow • trigger block diagram • MDC trigger • TOF trigger • EMC subsystem • Global Trigger • Present status and Outlook

  3. General:Estimation of event rate • Purpose of trigger system: • to accept all interested events • to rejects as much background as possible • DAQ is sustainable • With good design of MDC,TOF and EMC trigger, • we estimate that • total trigger rate • = good event rate (~2000, LBEPCII = 1  1033 cm-2 s-1) • + bhabha rate (~800,to be pre-scaled) • + cosmic event rate (<200,from 1500) • + beam background rate (<2000,from 13MHz) • = ~ 4000 Hz Fig:Backgrounds rate vs beam current At BESII/BEPC

  4. General:design rules • Pipeline processing must be used in trigger • Multi-bunches(93 in the ring) • small bunch spacing(8ns) =>Latch-process-decision mode not possible in 8ns) • Latency of trigger signal necessary • 3.2 s • No dead time in trigger system • Most recent technology will be used

  5. Time Reference Detector 0 s FEE pipeline Level 1 3.2s Readout buffer PowerPC switch Ev.Filter Farms Disk General: trigger system in data flow • Hardware trigger + software filter • FEE signal splitted: trigger + FEE pipeline • FEE pipeline clock 40MHz • Level 1(L1): 3.2s • FEE Control Logic checks L1 with FEE pipeline clock • L1 YES: moves pipeline buffer data • L1 No: • overwritten by new data BESIII FEE pipeline and Data flow

  6. Block Diagram of BES III Trigger Global Trigger Logic TOF DISC Hit/Seg Count Track Match MDC DISC Track Seg. Finder Track Finder DAQ Energy Balance EMC TrigSum TC Sum Etotal Energy L1P Cluster Counting MU DISC Mu track CLOCK RF TTC 3.2 s

  7. MDC Trigger-Signals Nswires 9008 N axial 4008 N stereo 5000 N layers 47 Nlaxial 19 Nlstereo 28 N pivot cells ax 92/116/224/320/320 N pivot cells st 48/72/160/192/224/256/288 N spcells/sector 32/16

  8. BLT 9008 2008 TSF cards On FEE TRK CNT GTSF Axial& stereo PTD/TF MDC trigger schemes GLT • Scheme A(AX only): • TSF + TF + TRKCNT • Scheme B(AX+ST): • TSF + GTSF +BLT+PTD+TRKCNT

  9. TSF(Track Segment Finding) Pivot layer Ideal case: same cells,high Pt Real case simulation These data is used for TS Finding

  10. TSF-Daughter Board Block Diagram 8 TSF Daughter Board 1-5 driver Left Neighbour 1-3 rec (LVPECL/LVDS) FPGA 32 8 8 Track segment finding stretcher Programable delay Outputs driver Inputs (LVPECL/LVDS) (LVPECL) 8 receiver Left Neighbour 1-5 driver 1-3 (LVPECL/LVDS) VME R/W Test and Control Commands 8

  11. From O BLT GTSF R To Algorithm g 2 to1 GLT a t e Control IN DAQ OUT Mem Mem Mem Mem GTSF(TSF grouping) and BLT(Binary Link Track) BLT Long track AX-AX: N=3 AX-ST: N=3 ST-ST: N=5 SPC: SL1-2:1/16 SL5-11:1/32 BLT Short track

  12. MomentumDiscrimination(PTD)/TF) • PTD/TF Long track: • Reference layer SL11 • SL7,SL4 and SL3 • 4 / 4 or 3 / 4 • PTD/TF Short track: • Reference layer SL7 • SL4 and SL3 • 3 / 3 or 2/3 SL11 SL7 SL4 SL3

  13. MDC trigger simulation • FORTRAN code • MDC structure + hits • Trigger scheme • Tasks: • Feasibility of trigger scheme • Trigger efficiency study • Wire in-efficiency influence study • Backgrounds rejecting ability study • Production of configuration data • Track Segment Finding • Track Finding/PTD

  14. Trigger efficiency vs Pt and wire efficiency Configuration: Pt > 120 MeV TSF:Ncomb=8 TSF:Ncomb=24 tracks with Pt>130MeV + Weff>95% TrigEff>95%

  15. MDC background rejection • very good rejection of artificial cosmic rays 10cm away from vertax(100% when requires Nltrk_ptd>1) • Rejection for beam backgd understudy. Result to be given after inputs from beam background simulation is avalable

  16. TOF Trigger PMT 88 TOFB PMT PMT 88 TOFB PMT 48 48 TOFE TOFE Leading Leading Mean Edge Disc Timer Edge Disc Disc. Leading Leading Disc. Mean Edge Disc Edge Disc Timer L &(L or L ) 1i 2i-1 2i+1 TOF Trigger Master Trigger Hit count and Timing topology logic

  17. EMC trigger Barrel: θ×φ=56×144 = 8064 Endcap: 120、120、120、96、 96、96、84、84、84 =1800 Basic trigger unit( trigger cell): sum of 24 crystals outputs

  18. EMC Simulation • <20% difference acceptable • Gain adjustment for each crystal+PD+PreAmp chain • Trigger Cell should be at least 4X4 =16 crystals. • 4X6=24 is taken

  19. BESIII EMC trigger scheme FEE 8ch sum Gain Adj.

  20. From TOF Trigger From BEMC Trigger From MDC Trigger From EEMC Trigger TOF Track Distribution EEMC Track Distribution BEMC Track Distribution Input Signals Delay Input Signals Delay Input Signals Delay Input Signals Delay Barrel Track Match Eadcap Track Match Matched Track Count To Main Trigger Controller Track Matching scheme

  21. Programmable Input Signal Delay Programmable Trigger Event Decision Trigger Conditions E-TYPE Programmable Pre-scale Multi-Scaler Reset Trigger EVT INIT TOF-T Trigger Controller L1 EMC-T CHK Trigger Signals Distribution EEMC-T To TRG Sub-system BUSY Clock Processor RF To Electronics TDC Global Trigger (GLT) • Inputs: sub-detector conditions • Time adjustment • trigger table • Pre-scaling of some event types

  22. Trigger conditions

  23. CLK GEVT L1 3s Tdead Tlife BUSY CHK TRG#=256 500ns Timing and handshaking with DAQ • Trigger pipeline clock • fRF= 499.8 MHz • f fRF /12  40MHz • Blocking of L1 of 3s required by Electronics fro peak finding • #TRG error checking with CHK signal

  24. Present Status and Outlook(1) • Trigger scheme is drafted and will be refined. • Trigger simulation goes well, will go further with physics and backgrounds study • Pipelined digital signal generator • Designed for other module testing. • Signal Sequence Programmable, signal length programmable • Readback Check, TTL/LVDS • high reliability • Experiment Board for VME Module Design • Base on FPGA, to be used for testing other VME module’s functionality • Pipeline Clock Generater/Divider Experiment done • VMS BUS Display Prototyped. Manual Controller in Circuit design • Digital programmable signal delay module is under debugging. • MDC TSF board is modeled in FPGA with 32 inputs, and simulated, will begin board design

  25. Present Status and Outlook(2) • Preliminary Design: Jul.2001 - End 2002 • Prototype of sub-system modules: Apr. 2002 - Dec.2003 • Test system and software:Oct.2002-Mar.2005 • Mass production: Oct.2003-Mar.2005 • Sub-system test: Jan. 2005-Sep.2005 • System integration/test Oct.2005-Dec.2005 • Cosmic-ray test:Jan.2006-May 2006 • Test run: End 2006

  26. Summary • Hardware trigger + software filter(on PC farm) • L1 latency: 3.2 s • Pipeline clock: 40 MHz • Monte Carlo simulation going well • backgrounds, MDC, EMC trigger schemes studies • Design scheme drafted • Some modules designed • Further/detailed designing undergoing • Welcome collaboration domestic and abroad

  27. Thanks!