Presentation #M2EZ ParkingWontaek Shin (M2-1)Shanshan Ma (M2-2)Nan Li (M2-3) Stage 1: 1/24/2006 Design Proposal Overall Project Objective: Design a chip as a part of a parking system that provides easy management and monitoring.
Status • Project chosen • Specifications defined • Verilog obtained/modified • Gate-Level Verilog • Test Benches • Schematic Design • Layout • Simulations
About the EZ Parking Our chip will: • Suggest you with the closest parking spot based on the vehicle-class, entry zone, and special needs • Calculate the total cost of parking depending on the varying prices, block of time, and vehicle-class
Marketing • Provides easier management of spot availability • Reduce traffic and avoid conflict in the parking lot • Designed in a unique way that can satisfy the needs of both drivers and parking lot management people
Algorithm Description • Each parking spot is equipped with a sensor that informs the central system of its availability. • The availability is stored in the SRAM. • The FSM decides the spot suggestion based on the information obtained from the SRAM and the customer. • The system marks the suggested spot temperately as occupied for 10 minutes. When the time is up, the spot will become available to other customers if no car is detected.
Design Blocks • SRAM • Easier to sustain data than DRAM but it’s much bigger in size • Holds 256 bits represents each parking spot • Adder / Subtracter • Use Ripple-Carry 8 bits unsigned adder/ subtracter • Spot Suggestion FSM • Inputs: 2 bits for 4 types of vehicle class 1 bit for 2 entry zones SRAM data • Outputs: 8 bits for spot location • Price Counter FSM • Uses subtracter to obtain total time, and then calculate the total cost by using the adder
Rough Transistor Count • Spot Allocation FSM ~4500 • Price Counter FSM ~2500 • Adder/ Subtracter ~2000 • SRAM ~5000 • Wait Block ~500 • Registers (inputs/outputs) ~500 • Total ~15,000
Alternative Designs • Refrigerator Manager • Cell-phone Monitoring • Health Watch
Problems & Questions • Unsure about complexity of SRAM and FSM • Having trouble finding Verilog code • Having trouble finding Short path algorithm • Is anyone else interested in joining our group?