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e + e - Collider Detector R&D

e + e - Collider Detector R&D. Status Report to US Japan Committee Daniel Marlow Princeton University June 5, 2001. Projects and Participants. Radiation hard readout for the Silicon Vertex Detectors Hawaii, KEK, Princeton, Tokyo Resistive Plate Chamber R&D

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e + e - Collider Detector R&D

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  1. e+ e- Collider Detector R&D Status Report to US Japan Committee Daniel Marlow Princeton University June 5, 2001 US Japan Meeting

  2. Projects and Participants • Radiation hard readout for the Silicon Vertex Detectors • Hawaii, KEK, Princeton, Tokyo • Resistive Plate Chamber R&D • KEK, Oregon, Princeton, SLAC, Tohoku • Vertex Detector R&D • Hawaii, KEK, Tokyo US Japan Meeting

  3. The SVD Readout Chip: the VA1 • 128 channels • Descendent of Viking (O. Toker et al., NIM A340 (1994) 572.) • AMS 1.2 um CMOS • Noise: US Japan Meeting

  4. New Directions • Incorporation of a fast trigger output. • Implementation in a sub-micron CMOS process to attain radiation hardness. US Japan Meeting

  5. Radiation Damage in MOS Transistors depends on ionization Reducing the oxide thickness by half is equivalent to cutting the dose by four. US Japan Meeting

  6. Process Comparison In the range of interest to BELLE, the noise vs. dose performance dramatically improves with decreasing feature size, as expected. US Japan Meeting

  7. Indeed, the 0.35-um process exhibits phenomenal radiation hardness. US Japan Meeting

  8. Single Event Phenomena Although the submicron processes appear to offer a total dose resistance that is considerably better than needed, one still needs to worry about “upsets” induced by ionization that is highly localized in space and time. This is our current focus. US Japan Meeting

  9. Single Event Upset and Latch-up • Single event upset (SEU) • Flip-flops flip when they should flop. • Single event latch-up (SELU) • Parasitic conduction paths form in the IC’s substrate. • Current draws large enough to destroy the chip through Joule heating can occur. • It is not clear how these effects will vary with feature size. Experimental measurements are needed. US Japan Meeting

  10. SELU Mitigation • According to the AMS measurements, the addition of an epitaxial layer during fabrication should improve the latchup performance of the VA1 chips. • We are refabricating the VA1 chip in the AMS 0.35 um CMOS with an epitaxial layer added. US Japan Meeting

  11. SEU Mitigation • The logic design of the VA1TA will incorporate 2 of 3 majority logic to detect and automatically correct SEU-induced errors. US Japan Meeting

  12. SEU, SELU, and the VA1 • Despite these precautions, it is important that we understand the effects. • We thus plan to carry out systematic comparisons between VA1’s implemented with varying line widths (and with & without an epitaxial layer). • IDEAS has submited two major engineering runs: • VA1 to AMS 0.35 m with epitaxial layer. • VA1TA to AMS 0.35 m with epitaxial layer. US Japan Meeting

  13. +++++++++++++++ _ _ _ _ _ _ _ _ _ _ _ +++ +++++ _ _ _ _ _ _ _ RPC Principles of Operation India Ink Signal pickup (x) Resistive plates 8 kV Signal pickup (y) India Ink Spacers A passing charged particle induces an avalanche, which develops into a spark. The discharge is quenched when all of the locally ( ) available charge is consumed. Before The discharged area recharges slowly through the high-resistivity glass plates. After US Japan Meeting

  14. RPCs are not robust. Dark currents arising from surface defects can cause a loss of efficiency. In the early days of Belle, serious efficiency losses were observed. Fortunately, these problems were resolved, but similar problems continue to plague the BaBar RPCs. Belle US Japan Meeting

  15. The RPC Death Spiral High dark currents induce a IR voltage drop across the resistive plates, which lowers the voltage across the gap, causing the chamber to slide off the efficiency plateau. Increasing the applied voltage doesn’t help since it merely results in increased dark current. US Japan Meeting

  16. Surface Defects in the Babar RPCs Work by J. Va’vra and H. Band of BaBar has shown that the linseed oil surfaces have suffered damage. US Japan Meeting

  17. Irreversible Current Increases Due to Stalagmite Formation US Japan Meeting

  18. Resistivity of Linseed Oil It appears that the linseed oil is not fully polymerized, which leaves it with a low resistance. Data from C. Lu (Princeton/BaBar) US Japan Meeting

  19. Oxygen Treatment C. Lu at Princeton (BaBar) found that oxygen causes the linseed oil to polymerize, which raises its resistivity and lowers the dark current. Before 5 days N2/O2 15 days N2/O2 Data from C. Lu (Princeton/BaBar) US Japan Meeting

  20. Is Oxygen a Long-Term Cure?Efficiency vs. Time Data from C. Lu (Princeton). Obtained using RPC extracted from BaBar. US Japan Meeting

  21. Pixel Detector R&D • Areas of study include bump-bonding studies & electronics development. • Original vendor list included GEC Marconi (Britain) and Advanced Interconnect Technology (AIT Hong Kong). • Marconi withdrew, so that bumps were pursued with AIT. • Test samples were 20 x 40 arrays of 50x 100 µm2 pixels. • Both “thick” (300 µm) and “thin” (100 µm) sensors were bonded to dummy readout chips were bonded. US Japan Meeting

  22. Sample Test Bonds Optical Image SEM Image US Japan Meeting

  23. IR Images IR images were used to examine the bonds, instead of the x-ray technique used by ATLAS. Good bonds Overpressed bonds To our knowledge, this is the first time that 100 µm-thick wafers have been successfully bump bonded in HEP. US Japan Meeting

  24. Summary • Development of SVD radiation-hard electronics is proceeding smoothly. • RPC studies are showing some interesting effects, but a clear solution to the bakelite RPC efficiency-loss problem is not fully in hand. • There are some promising results on thin-pixel detector bump bonding, but much remains to be done. US Japan Meeting

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