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eFLASH Optimization in SOCs Reliability Enhancement

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  1. eFLASH Optimization in SOCsReliability Enhancement B. GODARD 1 2 Encadrants : JM. DAGA 2 L. TORRES 1 G. SASSATELLI 1 1 2

  2. Thesis Context Flash Memory Resources Optimization in SOCs Comparison between non-volatile memories technologies Applications needs Ways to optimize in term of Performances, Power consumption, Density, Cost, Flexibility, … Emerging field: Yield/Reliability Redundancy architectures for yield Error Correction techniques (ECC) for reliability Today, mixed methodology to further enhance reliability / yield

  3. Summary eFLASH overview Reliability issues Enhancement methodology and architecture Mathematical modeling and gain Conclusions & Discussions

  4. Summary eFLASH overview Reliability issues Enhancement methodology and architecture Mathematical modeling and gain Conclusions & Discussions 4

  5. Flash Memory Overview Flash memory market is continuously growing More and more memory in SOC (SIA roadmap : 94% area in 2014) Technology shrinks Reliability requirements are increasing (1ppm objective for automotive products) 1. eFLASH overview

  6. The Floating Gate Concept Flotox architecture 1. eFLASH overview

  7. Flash Memory Architecture 1. eFLASH overview • An embedded flash memory is • an Embedded Flash Controller (test, security, access mode, additional features…) • a Flash Memory Module

  8. Flash Memory Module 1. eFLASH overview

  9. Summary eFLASH overview Reliability issues Enhancement methodology and architecture Mathematical modeling and gain Conclusions & Discussions 9

  10. Electronic Product Lifecycle 2. Reliability issues • Techniques to improve • Yield (Redundancy architecture) • Reliability (Error Correcting Codes) • But… • All redundancy not always used • Weakest bits are not always detected during test

  11. Reliability Characteristic Retention (>10 years without memory loss) Problem of Erratic and tail bits : Bit whose Vt change after some hours (random p = 10-6) Endurance (Nb. of write-erase performed before the first memory error) Improve max endurance to target automotive products 2. Reliability issues

  12. Summary eFLASH overview Reliability issues Enhancement methodology and architecture Mathematical modeling and gain Conclusions & Discussions 12

  13. Mixed Approach For Reliability Objective Propose a new design and methodology using ECC and/or redundancy to improve the reliability. Constraints Use the specificity of eFLASH Page Program/Erase oriented memory Analog states Minimize impact on application (timing, power consumption, area) Hypothesis Only one error can occur at time 3. Enhancement Methodology and Architecture

  14. Reliability Enhancement Techniques Error Detection and localization Post Write/Erase Comparison Analog Level Checker On line detection with ECC Fault Tolerance Mechanism Error Correction Redundancy Repair Refresh Analog States User policy to limit the impact on application Repair on error Delayed repair Scrubbing method 3. Enhancement Methodology and Architecture

  15. Redundancy Architecture Principle Replace the faulty elements of the main array with a fault free elements of redundancy Objective Make the logical matrix array fault free Architecture Need to implement additional pages and reconfiguration logic (CAM) 3. Enhancement Methodology and Architecture

  16. ECC Architecture Principle calculate and store a parity check information Objective Correct discrete random memory failures Encoder/Decoder Correct 1 error/word or Detect 2 errors/word Architecture Need to extent memory array to store parity Ex : 32 bits + 7 parity = 20% overhead 3. Enhancement Methodology and Architecture

  17. Analog Level Checker: Vt Analysis A read is made with a Vread low and a Vread high, the results are compared to detect errors. Not used in normal mode due to timing overhead. During scrubbing, cell with Vt in the forbidden zone are detected 3. Enhancement Methodology and Architecture Forbidden zone

  18. Example Of Reliability Policy Timing Diagram While there is redundancy Normal operation : on-line error detection and correction If error on write/erase : problem of endurance If error on read : problem of retention Replace with row redundancy Scrubbing : Error detection, Analog state analysis, If error or weak bits : problem of retention Replace with row redundancy If no redundancy : on-line error detection and correction only 3. Enhancement Methodology and Architecture time Scrub Normal operation

  19. Reliability Logic Wrapper ECC and Redundancy Reliability Logic Wrapper 3. Enhancement Methodology and Architecture

  20. Summary eFLASH overview Reliability issues Enhancement methodology and architecture Mathematical modeling and gain Conclusions & Discussions 20

  21. The Former Example 1 word = 1 row 100 words Architecture Redundancy ECC + Red. ECC + Red. For What ? Red. for Yield Red. for Yield ECC for Rel. Red. for Yield & Rel. ECC for Rel. On 1st Yield Error 100 % (Red.) 100 % (Red.) 100 % (Red.) On 2nd Yield Error 100 % (Red.) 100 % (Red.) 100 % (Red.) Repair Rate 100% 100 % 100 % On 1st Rel. Error 0% 100 % (ECC) 100 % (Red.) On 2nd Rel. Error 0% 99 % (ECC) 100 % (ECC) Reliability Rate (0ppm would mean 100%) 0% 99 % 100 % Commentary Not efficient One redundancy line does not serve and ECC capacity correction begins to decrease unnecessarily ECC used when there is no more redundancy row. The scheme prevent from errors undetectable during test 4. Mathematical Modeling and Gain

  22. Reliability Evaluation 4. Mathematical Modeling and Gain 99.999% 100% Mean time to failure gain: Time to failure gain to have 1 defective memory among 1000 (R=99.999%): 1 Mbits Array ECC 5 red. rows Error Probability = 10-6 80% 60% Reliability 40% ECC + Red Red 20% Nothing ECC 0% Time (au)

  23. Summary eFLASH overview Reliability issues Enhancement methodology and architecture Mathematical modeling and gain Conclusions & Discussions 23

  24. Conclusions and Discussions Topic identified : RELIABILITY Automotives objectives, reliability growing constraints. Architecture not optimized (separated use of ECC and redundancy). New reliability enhancement methodology developed Combines 1 Error Correction Code and redundancy. Uses specificity of Flash : Analog Level Checker. Other methodologies can be implemented Online correction and repair using error detection mechanism, analog level checker and redundancy. Future work Depending on the application needs, formalize the architecture and methodology to use Evaluate cost / performance (area, timing, power consumption)

  25. eFLASH Optimization in SOCsReliability Enhancement B. GODARD 1 2 Encadrants : JM. DAGA 2 L. TORRES 1 G. SASSATELLI 1 1 2

  26. 23rd IEEE VLSI Test Symposium May 1-5, 2005 – Palm Springs, CA, USA Architecture Performances • Examples • 1Mbits = 32 bits x 32768 words, 1024 pages, 64 words/page • Tread = 20ns, Tload = 20ns • Twrite_page = 2ms, Twrite_fuse = 1ms • ECC • Timing : Transparent for user, + 10% Tread (few ns) • Area : Overhead +20% • Redundancy • Area : Overhead < 3% • Repair Procedure • Timing : Trepair = 10 ms to write 10 fuses + ~2 ms to write page • Scrubbing • Timing : Tscrub = 1.31 ms to make Vt analysis