JAZiO I/O Switching Technology

1. JAZiO I/O Switching Technology

2. API HAL Topology Protocol Link Layer Logical Spec Electrical Spec Transport Spec Physical Layer Switching Technology Why Is Switching Technology Important? What Makes I/O? Switching Technology Determines I/O Performance Switching Technology Product Performance I/O performance may determine:

3. Switching Technologies • Dominant switching technologies today: • Differential • Pseudo-Differential • JAZiO technology is now available to challenge these current leaders

4. Transmitter Receiver + Data0 Data0 - Latching + DataN DataN - + CLK - Differential Used in: HyperTransport RapidIO SPI-4 Phase 2 LVDS Serial Channels Etc. • Fully differential receiver • Great for simultaneous switching • But two pins per data bit

5. Transmitter Receiver Data0 Data0 Latching DataN DataN VREF + CLK - Pseudo-Differential Used in: GTL PCI AGP SPI-4 Phase 1 Rambus RSL DDR Etc. • Constant VREF • Less-precise receiver • One pin per data bit

6. Transmitter Receiver Data0 Data0 DataN DataN VTR VTR VTR- JAZiO Technology Can be used: Anywhere that Pseudo-Differential Or Differential Are used Except Serial Channels • Voltage/Timing References • Two differential receivers per bit • One pin per data bit

7. Pseudo- Differential Differential JAZiO R R R R R R D0 VREF D0- D0 D0 D15 D15 CLK- CLK VTR- CLK- D15 VTR D15- CLK 34 Pins 18 Pins 19 Pins Three I/O Switching Technologies 16 Bits of Each

8. VTR- Provide alternating Voltage/Timing References switching at the data rate VTR Data is driven coincidentally with these VTRs Data Input Two Differential Comparators are used The Blue Box selects the right comparator One Bit Time Next Bit Time out in A VTR XorA in Data Input Data Output B in in VTR- out XorB Per Bit VTR SL VTR- Steering Logic SL- VTR Per 4 Bits JAZiO Solution Two White Papers at www.jazio.com Like Differential except: • VTR stands in for all the complements going in one direction • VTR- stands in for all the complements going in the other direction

9. The receiver cell is: 22um x 55um (Including routing channels) A pad cell is: 70um x 80um A JAZiO receiver is 22% of the area of a bonding pad

10. JAZiO vs Differential • So is JAZiO like Differential except with one pin per data bit? • No, it’s better than Differential because it has a larger data eye when attenuation and ISI jitter are present

11. Source Destination Source Destination Midpoint Attenuation/ISI Lone Pulse Signal at Destination is Centered Around the Midpoint Continuous Pulses

12. Continuous Pulse EYE Lone Pulse EYE Pseudo-Differential VREF DATA DATA- Differential MIDPOINT DATA VTR JAZiO MIDPOINT DATA Data Eye with Attenuation/ISI ~40% Attenuation Signals driven the same for all three technologies JAZiO Has MUCH Larger Worst-Case Data Eye

13. JAZiO vs Differential • So is JAZiO like Differential except with one pin per data bit? • No, it’s better than Differential because it has a larger data eye when attenuation and ISI jitter are present • A larger data eye can be used to: • Increase data rate • Reduce power • Increase robustness • Reduce complexity • Or all four!!!

14. Parallel vs Serial Interface • JAZiO is for parallel interfaces • Some claim that high speed interconnect must be serial due to large bit-to-bit skew • This leads to encoded serial data on a differential pair and, sometimes, bundles of serial channels • Also leads to complexity, power, and large latency • JAZiO can deal with skew and retain the benefits of low latency, parallel interface

15. JAZiO Deals with Skew • JAZiO is inherently better able to deal with skew because data eye opens and closes when data crosses VTR not the midpoint

16. Early Data Late Data No-Skew Data Midpoint Level JAZiO VTR Eye Opening Variance Differential or Pseudo-Diff Eye Opening Variance Bit-to-Bit Skew VREF NOTE: Same Variances At Trailing Edge • Signals Driven • Identically For: • JAZiO • Differential • Pseudo-Diff CONCLUSION: JAZiO is Inherently More Immune to Skew

17. JAZiO Deals with Skew • JAZiO is inherently better able to deal with skew because data eye opens and closes when data crosses VTR not the midpoint • A JAZiO receiver monitor is available which can be used to feedback to the source to equalize arrival time at the destination

18. Receiver Monitor out in A VTR XorA in Data Input Data Output B in in VTR- out XorB JAZiO Receiver Monitor XORs Provide Receiver Monitor (Feedback to Source) See White Papers at www.jazio.com Can Detect Marginalities In System During Operation Before Failure

19. JAZiO Deals with Skew • JAZiO is inherently better able to deal with skew because data eye opens and closes when data crosses VTR not the midpoint • A JAZiO receiver monitor is available which can be used to feedback to the source to equalize arrival time at the destination • JAZiO can use two-VTR pairs offset in time and tuning cycles can be used to select the best pair on each bit

20. R Data Out Data In Select R R2 VTR1 VTR1 VTR2 VTR2 Destination Deskew withTwo VTR Pairs See White Papers at www.jazio.com VTR Pairs offset in time selected using receiver monitor

21. Parallel vs Serial • A serial channel at 10 Gbps likely uses a differential pair and transmits 10 bits for every 8 bits of data (encoding) • Actual data rate per pin is 4 Gbps with huge die size, latency, and complexity penalties • JAZiO second generation provides same data rate per pin without die size or latency penalty – and is easily expanded as wide as desired Conclusion: No need for serial to invade the traditional domain of parallel buses

22. Switching Technology Enhancements Pre-E, Deskew, … Engineering Finished Product Enhancements Pre-E, Deskew, … Lots of Engineering Mediocre Product Small Eye 1 Pin/Bit Enhancements Pre-E, Deskew, … Lots of Engineering Expensive Product Medium Eye 2 Pins/Bit Less Engineering Large Eye 1 Pin/Bit What’s Needed for Finished Product? Data Eye Pins/Bit Pseudo-Diff Technology Differential Technology JAZiO Technology Enhancements Pre-E, Deskew, … Great Product

23. DATA (16) PAT GEN PAT GEN DRVRs RCVRs VTR (2) COMP 9” RING OSC BER MASTER SLAVE M/S M/S First Ever JAZiO Silicon Results Demo Chip: 0.18u TSMC, Standard ESD Enhancements: No pre-emphasis, encoding, or deskew Package: 120 Pin TQFP, 5nH Center-8nH Corner, <$1.00 PC Board: FR4, No isolation between signals Lowest cost, Highest availability components Previous highest known data rate with these conditions: <400 Megabits/sec/pin

24. Results VTR- VTR Power = 20 mW/bit Skew = 285 pS Data Rate = 1.5 Gigabits/Sec/Pin

25. 6 Gb/sec/pin 3rd Generation Deskew Pre-emphasis Dual VTR 0.10u + FC BGA Data Rate Per Pin 4 Gb/sec/pin 2nd Generation Deskew Simple Pre-emphasis 0.13u + BGA 2 Gb/sec/pin 1st Generation Basic JAZiO 0.18u + BGA 2001 2003 2005 Time JAZiO Roadmap

26. Announcements • Dolphin Technology (www.dolphin-ic.com) • JAZiO design services partner • Developing Super PHY with JAZiO technology • Alliance Semiconductor (www.alsc.com) • 1st JAZiO licensee • Developing high BW SRAM with JAZiO interface • Sampling in Q2, 2002

27. Summary • JAZiO is basic I/O technology from which excellent parallel buses can be built • Using JAZiO, parallel buses can achieve very high performance – no need to move to serial buses • JAZiO technology, with large data eye and pin efficiency, is the highest performance and lowest cost technology available