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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Low-Power Logic Families Pass-Transistor Logic. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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  1. ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsLow-Power Logic FamiliesPass-Transistor Logic Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5970-001/6970-001 Lecture 14

  2. Low-Power Logic Styles • Pass transistor logic • Dynamic logic • Domino logic • Adiabatic and charge recovery logic • Asynchronous logic • Logic restructuring ELEC 5970-001/6970-001 Lecture 14

  3. Pass-Transistor Logic • Requires fewer transistors • Smaller area • Reduced capacitance • Reduced energy and power ELEC 5970-001/6970-001 Lecture 14

  4. AND Gate B A F = AB 0 Need 4 transistors instead of 6 for CMOS gate. ELEC 5970-001/6970-001 Lecture 14

  5. Reduced Voltage Swing IN Vx = VDD – Vtn OUT VDD = 2.5V n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ ELEC 5970-001/6970-001 Lecture 14

  6. Spice Simulation 3.0 2.0 1.0 0.0 IN Vx Voltage, V OUT 0 0.5 1.0 1.5 2.0 Time, ns J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. ELEC 5970-001/6970-001 Lecture 14

  7. Voltage Transfer Characteristic (VTC) of AND Gate B A F = AB 0 n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ ELEC 5970-001/6970-001 Lecture 14

  8. VTC: Spice Simulation 3.0 2.0 1.0 0.0 IN VDD – Vtn B = VDD A = 0 → VDD F, V A = VDD, B = 0 → VDD A = B = 0 → VDD OUT 0 0.5 1.0 1.5 2.0 2.5 Vin, V ELEC 5970-001/6970-001 Lecture 14

  9. Energy If this voltage is insufficient for turning the pMOS Transistor in inverter off, leakage power will be consumed. 0 → VDD Vout VDD = 2.5V i(t) CL T T E0→1 = ∫ P(t) dt = VDD ∫ i(t) dt 0 0 VDD-Vtn = ∫ CL dVout = CL VDD (VDD – Vtn) 0 ELEC 5970-001/6970-001 Lecture 14

  10. Ways to Reduce Leakage • Level restoration • Multiple-threshold transistors • Transmission-gate logic ELEC 5970-001/6970-001 Lecture 14

  11. Level Restoration VDD Level restorer B Vout A CL Switching threshold = VDD/2 Level restorer device should be weaker than the nMOS pass transistor. Otherwise, VDD → 0 transition at Vout will be impossible. ELEC 5970-001/6970-001 Lecture 14

  12. Multiple-Threshold Transistors • Use zero-threshold pass-transistors. • Use high-threshold transistors in all other gates. • This can cause leakage through multiple gates. ELEC 5970-001/6970-001 Lecture 14

  13. Leakage Through Zero-Threshold Transistors Zero or low-threshold transistors 1 0 Leakage current path 0 1 ELEC 5970-001/6970-001 Lecture 14

  14. Transmission-Gate Logic • Provides both power and ground levels. • Good design, except needs more transistors. Inverting multiplexer A S B S’A’ + SB’ ELEC 5970-001/6970-001 Lecture 14

  15. Transmission-Gate XOR B AB’+A’B A ELEC 5970-001/6970-001 Lecture 14

  16. Synthesis of PTL Shannon’s expansion: Z = AB + BC + AC = A(B+BC+C) + A’(BC) = A(B+C) + A’BC = A[B+B’C] + A’[BC] 1 C C 0 1 0 1 0 B 1 0 A Z ELEC 5970-001/6970-001 Lecture 14

  17. Pass-Transistor Cell ELEC 5970-001/6970-001 Lecture 14

  18. Synthesis of Z = A’B’ + BC’ + A’C A 0 B C Z ELEC 5970-001/6970-001 Lecture 14

  19. Synthesis of Z = A’ + BC’ + B’C C C’ 0 B B’ A A’ Z ELEC 5970-001/6970-001 Lecture 14

  20. Synthesis of Z = AB’C’ + A’B’C C’ C 1 B B’ A’ A Z ELEC 5970-001/6970-001 Lecture 14

  21. CPL: Complementary Pass-Transistor Logic • Every signal and its complement is generated. • Gates are static, because the output is connected to either VDD or GND. • Design is modular; same cell can produce various gates by simply permuting the input signals. • Also called differential pass-transistor logic (DPL) ELEC 5970-001/6970-001 Lecture 14

  22. A CPL Cell ELEC 5970-001/6970-001 Lecture 14

  23. CPL Cell Used As AND/NAND B B’ ABA’ B’ Z = AB Z=(AB)’ ELEC 5970-001/6970-001 Lecture 14

  24. CPL Cell Used As OR/NOR B’ B ABA’ B’ Z = A+B Z=(A+B)’ ELEC 5970-001/6970-001 Lecture 14

  25. CPL Cell Used As XOR/XNOR B’ B AA’A’ A Z = AB’+A’B Z= AB+A’B’ ELEC 5970-001/6970-001 Lecture 14

  26. References • G. R. Cho and T. Chen, “On the Impact of Technology Scaling on Mixed PTL/Static Logic,” Proc. IEEE Int. Conf. Computer Design, 2002. • R. Zimmermann and W. Fichtner, “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic,” IEEE J. Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997. ELEC 5970-001/6970-001 Lecture 14

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