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CPU Segment Registers: Cache Mechanism & Control Bits

Explore how segmentation attributes are cached within CPU segment registers, including the hidden portions of CS, SS, DS, ES, FS, GS, TR, LDTR, GDTR, IDTR. Learn about real-mode and protected-mode memory addresses, segment descriptors, and segment-descriptor format. Discover the role of segment-base address, segment limit, and Intel instruction format in defining memory access. Gain insights into using prefix bytes to override default settings and modify instruction execution in IA-32e mode. A program example illustrates the impact of illegal values in FS and GS segment registers on executing ROM-BIOS service functions.

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CPU Segment Registers: Cache Mechanism & Control Bits

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  1. Segment-registers’ hidden bits A look at how segmentation attributes are cached within the CPU’s segment-registers

  2. CPU segment-registers 16-bits CS Hidden portion of CS SS Hidden portion of SS DS Hidden portion of DS ES Hidden portion of ES FS Hidden portion of FS GS Hidden portion of GS TR Hidden portion of TR LDTR Hidden portion of LDTR GDTR GDTR IDTR IDTR

  3. “Hidden” part of segment-registers selector segment base segment limit access rights The “invisible” parts of a segment-register The programmer-visible part of a segment-register

  4. Real-Mode Addresses segment offset Logical Address: x16 + While in Real-Mode, the memory-segments are all 64-kilobytes in size (and readable/writable) Physical Address: Operand’s effective address

  5. Protected-Mode Addresses segment-selector segment-offset Logical Address: Segment Descriptor Table descriptor Validity is checked by CPU Segment Base-address descriptor + (also Segment-Limit and Access Rights) descriptor descriptor Physical Address: Operand’s effective address

  6. Segment-Descriptor Format 63 32 Base[31..24] G D R S V A V L Limit [19..16] P D P L S X C / D R / W A Base[23..16] Base[15..0] Limit[15..0] 0 31 Several instances of this basic ‘segment-descriptor’ data-structure will occur in the Global Descriptor Table (and maybe also in some Local Descriptor Tables)

  7. EM64T TSS/LDTR descriptors 127 96 Reserved (must be 0) base[ 63..32 ] offset[63..32] Base[31..24] (if S=0) base[ 31.. 24 ] Reserved (must be 0) G D L A V L limit [19..16] P D P L 0 X Type C / D R / W base[ 23.. 16 ] base[ 15..0 ] limit[15..0] 31 0 Type: 1010 = LDT descriptor, 1001 = available TSS, 1011 = busy TSS

  8. 48-bit Register-Format 47 16 15 0 Segment Base-Address Segment Limit 32 bits 16 bits

  9. EM64T 80-bit Register-Format 79 16 15 0 Segment Base-Address Segment Limit 64 bits 16 bits

  10. Intel instruction-format maximum instruction-length equals 15 bytes prefixes opcode address mode address displacement address displacement 1, 2, or 3 bytes 0, 1, or 2 bytes 0, 1, 2, or 4 bytes 0, 1, 2, 4, or 8 bytes Prefix bytes are used to ‘override’ the processor’s current default settings: (1) selection of memory-operand segment-register (2) current default setting of operand’s width (3) current default setting of address’s width Or to modify the way in which the subsequent instruction will execute: (4) lock the bus for duration of instruction’s execution (5) conditionally reexecute a string-instruction (6) provide extra operand-selection bits (IA-32e mode)

  11. Mode-r/m and SIB bytes 7 6 5 3 2 0 mod reg r/m 7 6 5 3 2 0 scale index base

  12. ‘hangdemo.s’ • This program shows why ‘illegal’ values left in the FS and GS segment-registers can cause our demo-programs to ‘hang’ when leaving ‘protected-mode’ and then attempting to execute some ROM-BIOS service-functions

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