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EENG 449bG/CPSC 439bG Computer Systems Lecture 11 Power Issues and DVS . February 17, 2005 Prof. Andreas Savvides Spring 2005 http://www.eng.yale.edu/courses/eeng449bG. Announcements. Reading reference for this lecture

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EENG 449bG/CPSC 439bG Computer Systems Lecture 11 Power Issues and DVS


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    1. EENG 449bG/CPSC 439bG Computer SystemsLecture 11 Power Issues and DVS February 17, 2005 Prof. Andreas Savvides Spring 2005 http://www.eng.yale.edu/courses/eeng449bG

    2. Announcements • Reading reference for this lecture • J. Pouwese, K. Lagendoen, H. Sips, “Dynamic Voltage Scaling on a Low Power Microprocessor”, posted on the class website • Midterm date discussion & conflicts with other classes

    3. Why worry about power?Intel vs. Duracell • No Moore’s Law in batteries: 2-3%/year growth 16x 14x Processor (MIPS) 12x Hard Disk (capacity) 10x Improvement(compared to year 0) 8x Memory (capacity) 6x 4x Battery (energy stored) 2x 1x 0 1 2 3 4 5 6 Time (years)

    4. Current Battery Technology is Inadequate • Example: 20-watt battery • NiCd weighs 0.5 kg, lasts 1 hr, and costs $20 • Comparable Li-Ion lasts 3 hrs, but costs > 4x more

    5. Comparison of Energy Sources Assume 1mW Average as definition of “Scavenged Energy”

    6. Trends in Total Power Consumption source : arpa-esto • Frightening: proportional to area & frequency DEC 21164 microprocessor power dissipation

    7. Power Metrics in Microprocessors nJ/Instruction • Mostly for processors with the same instruction sets • Does not capture the effect of operand size (e.g 8-bit addition vs. 32-bit addition operations MIPS/Watt mA – common among component data sheets Remember:

    8. Modeling the Battery Behavior • Theoretical capacity of battery is decided by the amount of the active material in the cell • batteries often modeled as buckets of constant energy • e.g. halving the power by halving the clock frequency is assumed to double the computation time while maintaining constant computation per battery life • In reality, delivered or nominal capacity depends on how the battery is discharged • discharge rate (load current) • discharge profile and duty cycle • operating voltage and power level drained

    9. Battery Capacity from [Powers95] • Current in “C” rating: load current nomralized to battery’s capacity • e.g. a discharge current of 1C for a capacity of 500 mA-hrs is 500 mA

    10. Battery Capacity vs. Discharge Current • Amount of energy delivered is decreased as the current (rate at which power is drawn) is increased • rated as ampere hours or watt hours when discharged at a specific rate to a specific cut-off voltage • primary cells rated at a current which is 1/100th of the capacity in ampere hours (C/100) • secondary cells are rated at C/20 or C/10 • At high currents, the diffusion process that moves new active material from electrolytes to the electrode cannot keep up • concentration of active material at cathode drops to zero, and cell voltage goes down below cut-off • even though active material in cell is not exhausted!

    11. Battery Energy Consumers

    12. Processing Programmable Ps & DSPs (apps, protocols etc.) ASICs Memory Communication RF Transceiver Radio Modem Where does the Power Go? Peripherals Disk Display Power Supply DC-DC Converter Battery

    13. Power Consumption for a Computer with Wireless NIC

    14. Energy Consumption ofWireless NICs (Wavelan)

    15. Example: Power Consumption for Compaq’s iPAQ 206MHz StrongArm SA-1110 processor 320x240 resolution color TFT LCD Touch screen 32MB SDRAM / 16MB Flash memory USB/RS-232/IrDA connection Speaker/Microphone Lithium Polymer battery PCMCIA card expansion pack & CF card expansion pack • * Note • CPU is idle state of most of its time • Audio, IrDA, RS232 power is measured when each part is idling • Etc includes CPU, flash memory, touch screen and all other devices • Frontlight brightness was 16

    16. Microprocessor Power Consumption CMOS Circuits (Used in most microprocessors) Static Component Bias and leakage currents O(1mW) Dynamic Component Digital circuit switching inside the processor Dynamic Static

    17. Power Consumption in Digital CMOS Circuits - current constantly drawn from the power supply - determined by fabrication technology • short circuit current due to the DC path between the • supply rails during output transitions - load capacitance at the output node - clock frequency - power supply voltage

    18. Dynamic Voltage Scaling • What can you do to conserve power on a processor? • Dynamic power consumption is the dominant component • Example: Transmeta’s Crusoe processor

    19. DVS on Low Power Processor Number of gates Maximum gain when voltage is lowered BUT lower voltage increases circuit delay Dynamic Power Component Load capacitance of gate k Propagation delay Transistor gain factor CMOS transistor threshold voltage

    20. Voltage Scaling on LART • Dynamically lower the processor voltage and frequency to reduce power consumption • LART wearable board • StorngARM 1100 Processor 190MHz • Various I/O capabilities • 32 MB volatile memory • 4 MB non-volatile memory • Programmable voltage regulator

    21. Processor Envelope At 1.5V Max clock frequency 251MHz Min frequency the processor functions correctly is 59MHz

    22. LART Power Measurement Based on dhrystone benchmark • Note the measurement setup at • Different levels on the board • Always provide hooks for • measurement, testing and debugging • during your design. Both for • software and hardware!!! Total Power Consumption on the LART Platform

    23. System Support Requirements • To manage DVS effectively, the computation requirements must be known in advance • Predictive scheme • Try to learn that behavior based on the computation profile • Better scheme: Applications should be power aware • Processor frequency and scaling should be changed without much delay • This is specific to each processor • 150us for the LART processor

    24. Example: Power Aware Video Playback • Annotate a H.263 video decoder with information on the clock speed required to decode a known video sequence • Using a 12.6s video, 15fps • Power consumption measurements for LART • No-DVS: 198mW for CPU, 207mW for memory subsystem • DVS: 100mW for CPU and 204mW for the memory subsystem • 2X improvement, but 25% improvement when memory accesses are considered

    25. LART Memory Performance • Memory access is optimal when high resolution memory access timing is available • For LART the optimal memory pattern: • 148MHz • 92 MB/s memory bandwidth • Power consumption 514.2mW • Energy cost 5.6mJ/MB

    26. Memory Subsystem Power Consumption – Read Operation Optimal memory access waveforms Power consumption Memory Bandwidth

    27. Energy breakdown for read(based on 1MB read) Regulator Loss-factor

    28. Power Breakdown for H.263 Decoder

    29. Reducing Power Consumptionis a multilevel task! • Physical layer • Technology – reduce the surface of CMOS circuits • Architecture/IC level • Several optimizations in the design (e.g parallelism and pipelining) • Provide hooks for software driven power management (e.g different power modes and clock speeds) • OS Level • Smart schedulers, interval schedulers, DVS • Application Level • Power aware applications that worn the OS and the hardware about the features needed during application lifetime • Sleep modes and DVS driven by applications • Network Level • Networked devices may be able to apply low duty cycles, in which some of the devices are asleep and others are awake

    30. Conclusions • Interval based schedulers not so efficient • Interval-scheduler – reduce voltage after a pre-specified idle period is detected • Better leverage of DVS when the processor is aware of the application requirements • Illustrated with the H.263 encoder • Monitor different power consumption profiles across different sections of the platform and use them to make clever decisions about power-management • What is missing: • Comments on power regulator efficiencies…

    31. Announcements • Need to start deciding on the final projects. • We need to discuss these with you individually at the end of class • One page detailed proposal by March 3 • This should include • 1 paragraph motivation and description of your project • 1 paragraph on the approach you are going to use and the tools • 1 paragraph on evaluation • What is the strategy you will use to evaluate the performance of your project.

    32. DVS Example • Consider a processor with DVS • Frequency range 250 – 59MHz • Supply Voltage range 0.8V (@49MHz) and 1.5V (@250MHz) • Assume that the processor can compute at 1 MIPS per MHz.

    33. DVS Example 1 • What is the maximum energy saving the processor can achieve with dynamic voltage scaling? • What is missing?

    34. Task Execution Energy Cost • A certain task needs to run on the processor. The task requires 200 Million Instructions to complete. • Which power level will be the most efficient?

    35. Power Consumption on Embedded Processors • Different core I/O from Peripheral I/O – numbers here • Cores scaling down to 0.8V. 1.8V devices are becoming common • General Purpose I/O interfaces still at 3.0 – 3.3V • Makes power supply harder, additional regulator inefficiency • Sleep modes and associate cost of sleep and recovery SA-1100 modes • Need time and energy to transition between states

    36. Example: SA-1100 CPU 400 mW • RUN • IDLE • CPU stopped when not in use • Monitoring for interrupts • SLEEP • Shutdown on-chip activity RUN 10 ms 90 ms 10 ms 160 ms IDLE SLEEP 90 ms 50 mW 0.16 mW

    37. Duty Cycling: Exploiting Sleep Modes • Imagine a processor with max power consumption 120mW • Power supply voltage 2.5V • We need to power the device form a 2000mAh battery for 1 year • Sleep mode draws 20uA current • What is the duty cycle the device needs to operate at to last for at least 1 year?

    38. Duty cycling • 1 year has 365 x 24 = 8760 hours

    39. Voltage Reduction is Better • Example: task with 100ms deadline, requires 50ms CPU time at full speed • normal system gives 50ms computation, 50ms idle/stopped time • half speed/voltage system gives 100ms computation, 0ms idle • same number of CPU cycles but 1/4 energy reduction T1 T2 T1 T2 Same work, lower energy Speed Idle Task Task Time

    40. Problem with Voltage Reduction • Voltage gets dictated by the tightest (critical) timing constraint • not a problem if latency not important • throughput can always be improved by pipelining, parallelism etc. • but, real systems have bursty throughput and latency critical tasks Solution: dynamically vary the voltage!

    41. Variable Supply Fixed Supply T T frame frame Active Idle Active 2 2 × E = 1/2 CV × E = 1/2 C(V /2) = 1/4E fixed dd var dd fixed 1.0 0.8 N o r m a l i z e d o 0.6 P w e r 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0 Varying the Supply Voltage Fixed Supply from [Gutnik96] (VLSI Symposium) Variable Supply Normalized Workload

    42. XYZ Node Frequency Scaling

    43. Code Optimizations for Low Power • High-level operations (e.g. C statement) can be compiled into different instruction sequences • different instructions & ordering have different power • Instruction Selection • Select a minimum-power instruction mix for executing a piece of high level code • Instruction Packing & Dual Memory Loads • Two on-chip memory banks • Dual load vs. two single loads • Almost 50% energy savings

    44. Code Optimizations for Low Power (contd.) • Reorder instructions to reduce switching effect at functional units and I/O buses • E.g. Cold scheduling minimizes instruction bus transitions • Operand swapping • Swap the operands at the input of multiplier • Result is unaltered, but power changes significantly! • Other standard compiler optimizations • Intermediate level: Software pipelining, dead code elimination, redundancy elimination • Low level: Register allocation and other machine specific optimizations • Use processor-specific instruction styles • e.g. on ARM the default int type is ~ 20% more efficient than char or short as the latter result in sign or zero extension • e.g. on ARM the conditional instructions can be used instead of branches

    45. Minimizing Memory Access Costs • Reduce memory access, make better use of registers • Register access consumes power << than memory access • Straightforward way: minimize number of read-write operations, e.g. • Cache optimizations • Reorder memory accesses to improve cache hit rates • Can use existing techniques for high-performance code generation

    46. Low-power Software Strategies • Code running on CPU • Code optimizations for low power • Code accessing memory objects • SW optimizations for memory • Data flowing on the buses • I/O coding for low power • Compiler controlled power management CPU Cache Memory

    47. How can power consumption be reduced at the circuit design level inside a processor?

    48. Critical path delay: Tadder + Tcomparator = 25 ns • Frequency: fref = 40 MHz • Total switched capacitance = Cref • Vdd = Vref = 5V • Power for reference datapath = Pref = CrefVref2fref Example: Reference Datapath from “Digital Integrated Circuits” by Rabaey

    49. The clock rate can be reduced by x2 with the same throughput: fpar = fref/2 = 20 MHz • Total switched capacitance = Cpar = 2.15Cref • Vpar = Vref/1.7 • Ppar = (2.15Cref)(Vref/1.7)2(fref /2) = 0.36Pref Parallel Datapath from “Digital Integrated Circuits” by Rabaey

    50. fpipe = fref Cpipe = 1.1Cref Vpipe = Vref/1.7 • Voltage can be dropped while maintaining the original throughput • Pipe = CpipeVpipe2fpipe = (1.1Cref)(Vref/1.7)22fref = 0.37Pref Pipelined Datapath from “Digital Integrated Circuits” by Rabaey