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Generic Reconfigurable Computer

Why is Building RCCs for Space So Hard? MAPLD 2005 J. R. Marshall joe.marshall@baesystems.com 703-367-1326. Generic Reconfigurable Computer. Micro-Controller Memory. Micro- Controller. Hi-Speed Data Connections. Volatile Reconfigurable Logic Arrays. System Bus Or Fabric. System

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Generic Reconfigurable Computer

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  1. Why is Building RCCs for Space So Hard?MAPLD 2005J. R. Marshalljoe.marshall@baesystems.com 703-367-1326

  2. Generic Reconfigurable Computer Micro-Controller Memory Micro- Controller Hi-Speed Data Connections Volatile Reconfigurable Logic Arrays System Bus Or Fabric System /Memory Bridge Internal Memory or Control Bus Configure & Read-back Function Clocks Shared Data Memories Timing Configuration Memory 2

  3. Radiation Challenges • Total Ionizing Dose • Technologies Improving as Size Decreases • Single Event Effects • Getting Worse – Must Continue to be Focus • Current Mitigation • Fuse-Based (modular and configurable – not reconfigurable) • TMR Circuits • Readback, Check and Reload of Configuration Memory • Mix and Match of Appropriate Elements vs. Application • Future Mitigation • NonVolatile Radiation Hardened Configuration Memory • HBD or Radiation Hardened Memory and Logic 3

  4. Clocking • Special Emphasis Needed Here across Reconfigurable Elements • Many standard interfaces have built in Clocks • PLLs Enable Lower Speed Clocks except when data must be tagged to the highest Frequency • Fastest Needs are for Point-to-Point Connection • Must be able to share data across multiple devices on same clock cycle 4

  5. Infrastructure • Can Not Be Ignored • Common Infrastructure Block • Pre Tested I/Os • Internal “Application” Design Easier • Enables Mixing and Matching of Cores • Cores • Both Logic and Memory Elements • Need internal Connection Medium for Devices • Pre-tested • Parameterized as Much as Possible – increases Flexibility • Support Tools and Environment • Leverage COTS Tools • Overlap Mission Users with Developers to Maximize Ease of Use and Testing 5

  6. Challenges using Latest FPGAs • Current Reconfigurable FPGAs in Very High I/O (1000+ Pins) Packages • Maximum Capability Requires • Maximize Universal Interconnects • Maximize Thermal Paths • Maximize Thermal Cycling Capabilities • Maximize Modular Elements • Must be Space Qualifiable • Mechanical Challenges • High Density Reliable Pluggable Connectors • 3D Structures Per Element on Backplanes • Fabric Modularity on Backplanes (no SPOF) • Higher Density on Circuit Boards and Within Packages • Multiple Power Sources and Voltages • Thermal and Vibration Solutions • Design Complexity Challenges • Fine and Coarse Grain Cores and Designs 6

  7. Lessons Learned • Radiation Tolerance always a concern for Space • Must have more standard interfaces • Infrastructure will enable true reconfiguration – don’t forget mission user and operator training • Seldom does one processing technology fit all needs – i.e., mix from GPPs to FPGAs to ASICs • Must Always Lower Power, period. • Power, Thermal and Mechanical are true enablers for future progress 7

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