Introduction Part 2: Data types and addressing modes

IntroductionPart 2: Data types and addressing modes dr.ir. A.C. VerschuerenEindhoven University of TechnologySection of Digital Information Systems

Data type basics • High level data types must be mapped onto bit patterns which can be manipulated by the CPU The representation must be suchthat hardware is kept as simple as possible • Basic data types are stored in one word or fixed number of words (2, 4, 8: powers of two!) • Complex data types are not handled as a unit,the parts are addressed and manipulated separately

Data type determination • Generally the instruction determines thedata type, not the stored bit patterns themselves • Data type enforcing is done by high level compiler ! • ‘Tagging’ data with data type is possible • Requires extra memory bits for each data word • Data read must be type checked and/or converted This requires complex hardware and execution time!

Bit number N-1 N-2 2 1 0 2N-1 2N-2 22 21 20 Weight 128 64 4 2 1 For N=8 'Ordinals’: non-negative whole-numbers • Encoded by giving 'weights' to the bits in a word and adding the weights of the '1' bits together • Value range is 0..(2N-1) for N bit values,possibility of overflow and underflow ! • Standard operations:Add, Subtract, Multiply, Divide, Shift (= mul/div by 2N)

Bit number N-1 N-2 2 1 0 –2N-1 2N-2 22 21 20 Weight –128 64 4 2 1 For N=8 ’Integers’: generic whole-numbers • Encoding generally done using 'two's complement' • Value range is –(2N–1)..(2N–1 – 1) for N bit values,possibility of overflow and underflow ! • Other encodings can be used for integers:‘one’s complement’ or ‘sign and magnitude’ • Standard operations as ordinals (different shift right) Different check for overflow/underflow

Boolean logic values: one bit ‘true’/’false’ • AND, OR and XOR mostly done on whole words • Some processors can perform boolean operations on single bits in a word (using special instructions) • Compilers may use whole words for a boolean • Use specific bit patterns to denote true/false OR • Use only one bit in the word and disregard the rest OR • Use rules like 'all 0 = false, anything else = true' • Conditional jumps normally based on bit flags which indicate the last instruction’s result Zero, Positive/Negative, Carry/Borrow, Overflow....

‘Characters’: encoded readable text • Uses arbitrary bit pattern encoding: international standards like ‘ASCII’ needed • Truly international character sets require a large amount of separate characters (Japanese, Chinese !) • Only few operations make sense on characters • Comparing for equality is always possible • Comparing for higher/lower only if order is defined(an alphabet!) and encoded in the bit patterns • ’Block move' instructions handle character sequences

Bit number 2 1 0 7 6 5 4 3 Weight 0.5 0.25 0.125 –16 8 4 2 1 Binary fixed point values: fractions • Change the bit weights of ordinals or integers • Example with range –16..+15.875 in steps of 0.125 • The binary point can be placed arbitrarily • The minimum step size is fixed by this choice • Program must manage the position of the binary point, there is no hardware support ! True ‘real’ values are impossible

‘Floating point’: more precise • For a fixed number of bits, relative precision can be kept constant by moving the binary point value = base exponent• mantissa Base is a fixed number, normally taken as 2 Mantissa is the basic value represented by a binary fixed point notation • For base 2, mantissa range is normally [0..1) or [0..2) • Mantissa also encodes the sign of the complete value Exponent indicates by how much the mantissa is scaled to smaller (exp. < 0) or larger (exp. > 0) values

The IEEE 754-185 floating point standard • Lots of choices, a standard was needed ! Baseis taken 2 here Mantissa is given as sign-and-magnitude value • Separate sign bit • Magnitude as fixed point binary with range [0..2) Exponentis given as ordinal with fixed negative offset • Minimum and maximum exponent values are special cases for encoding zero, overflow etc.

Exponent Mantissa Value +/– 0 (two different zero notations !) 0 minimum (0..1) 'denormalised’ (close to zero, reduced precision) [1..2) illegal, not allowed [0..1) illegal, not allowed normal [1..2) normal value [0..1) illegal, not allowed 1 +/– 'infinity’ (may be result of overflow) maximum (1..2) 'Not a Number’ (NaN- to report/propagate errors) 'IEEE floating point' exponent values • Mantissa [0..1) only for minimum exponent • Mantissa [1..2) only for non-minimum exponent Leftmost bit of mantissa can be determined from exponent!

sign bit exponent <E bits> mantissa (magnitude) <M bits> single double IEEE format name: single double extended extended  11 bits  15 bits E 8 bits 11 bits  32 bits  64 bits M 23 bits 52 bits  –1022  –16382 minimum exponent –126 –1022 maximum exponent +127  +1023 +1023  +16383 unspecified unspecified exponent offset –127 –1023 stored stored MSB mantissa not stored not stored total width 32 bits  44 bits 64 bits  80 bits ‘IEEE floating point’ standard formats

for ‘interval arithmetic’ ‘IEEE floating point’ requirements (1) • Several rounding modes must be present • Round towards zero • Round towards negative infinity • Round towards positive infinity • Round 'towards nearest or even’ (balances errors) • A number of functions must be present too • Arithmetic: standard add, subtract, multiply and divide, but also remainder, square root, round-to-integer • Floating point  integer or decimal string • Compare operations (may return ‘not comparable’)

‘IEEE floating point’ requirements (2) • Precision of calculations must be very high • Results must really be rounded values of absolute precision calculations ! • Must be possible to round to lower precision if more than just single precision is provided • Needed to simulate low precision format calculations • Calculation errors must be logged and/or trapped • Can use ‘NaN’ to propagate error to end of calculation

address A[9] (word 2) 133 A[9] (word 1) 132 address R.r (word 2) 113 A[4] (word 2) 123 R.r (word 1) 112 scale (=2) A[4] (word 1) 122 R.q (boolean) 111 offset A[3] (word 2) 121 R.p (word) 110 base A[3] (word 1) 120 base Addressing arrays and records (structs) • Map them on sequence of memory words • Address the sub-parts separately ! A = array [3..9] of 'double-word' R = record p: word; q: boolean; r: 'double-word’ end; offset = 0 offset = 1 offset = 2 & 3 address = base + offset address = base + (index – 3)  scale (to get to word 1 of each 'double-word')

address 117 SP y (word) 116 BP (for s1) ,BP (for s1) BP for p1 115 SP SP BP (for s1), SP ret. addr. f1 114 SP SP SP SP x (value 3) 113 SP p (word) 112 BP (for p1) p (value 4) BP p1 caller 111 BP (for p1) ret. addr. p1 110 High level language stack ‘frames’ • The stack plays a major role in high-level languages • A 'base' (or 'frame' ) pointer ‘BP’ references parameters and variables stored on the stack procedure p1 var p: word; p := f1(3); end; 3: Push base pointer BP 4: SP  SP – size of parameter(s) 3: return from subroutine 1: Push parameter(s) 2: pop BP from the stack 4: Load BP with SP 5: use result value (from register) run subroutine (result  register) 5: SP  SP + size of variable(s) 1: Load SP with BP 2: Call subroutine function f1(x: word): word; var y: word; begin y := 1; f1 := x + y; end;

Basic adressing modes ImmediateADD #15The instruction includes the (constant!) data itself RegisterADD r1A register contains the actual data Absolute (or ‘Direct’)ADD [105]A directly specified (constant) address contains the data IndirectADD [r2]A register contains the address of the data Indexed (or ’Based')ADD [r4 + 14]A register and a fixed offset are added to address the data

Some addressing mode ‘extensions’ Automatic increment/decrementADD [r1++] • A register addresses the data and is modified • Register pointed to previous data item: pre-increment • Register pointed to next data item: pre-decrement • Register must point to next data item: post-increment • Register must point to previous item: post-decrement • The added/subtracted offset depends upon the data size Scaled indexADD [r2*4+123] • A register value multiplied by a scale factor (power of 2) and fixed offset are added to address the data • Used to access arrays with a fixed base position

Some really complex addressing modes Double indirectADD [[r3]] • A register contains the address of the address of the data • Some processors allow 'multiple indirect addressing’(with a flag bit indicating the last address) Scaled indexed based offsetADD [r1*8+r2+14] • Can access an array local variable inside a subroutine:r1 = array index, 8 = array entry size,r2 = base pointer, 14 = offset from the base pointer to start of the array

Final addressing mode remarks • Stack (relative) addressing uses the SP or BP registers in one of these modes as 'base' register • True RISC processors only know immediate, register and indirect addressing modes • The 'set' data type is generally implemented as a bitmap, using word-wide logical operations • Other high-level data structures are normally constructed in software ! Hardware implementation is difficultbut may be very attractive for speed !

Introduction Part 2: Data types and addressing modes