Tile HCAL VFE electronics development status. Dubna. APD 0. Orsay FLCHPY3. S&H. Mul. PrA. Sh. 20 Sept. HV. Dig. DATA. A P D 17. ADC AD7677 16 bit 1 µsec/ch. Yu. Musienko Erice 03.10.03. Yu. Musienko Erice 03.10.03. Reading FLC chip. Critical to the SH signal ±10nsec
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electronics development status
meeting in Dubna
End of 2003
Pilot boards production
LED calibr. Test?
APD V<400v generating on the board and tuning for each channel
APDG V<100v delivering on the board and tuning for each channel