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Tile HCAL VFE electronics development status

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Tile HCAL VFE electronics development status. Dubna. APD 0. Orsay FLCHPY3. S&H. Mul. PrA. Sh. 20 Sept. HV. Dig. DATA. A P D 17. ADC AD7677 16 bit 1 µsec/ch. Yu. Musienko Erice 03.10.03. Yu. Musienko Erice 03.10.03. Reading FLC chip. Critical to the SH signal ±10nsec

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Presentation Transcript
slide1

Tile HCAL VFE

electronics development status

Dubna

slide3

APD 0

Orsay FLCHPY3

S&H

Mul

PrA

Sh

20 Sept.

HV

Dig. DATA

A

P

D

17

ADC

AD7677

16 bit

1µsec/ch

slide5

Yu. Musienko

Erice 03.10.03

slide6

Yu. Musienko

Erice 03.10.03

slide7

Reading FLC chip.

  • Critical to the SH signal ±10nsec
  • Multiplexer switching time ≤100 nsec
  • 2. ADC on board is Ok.
  • 3. Data are in CAMAC.
  • 4. Now tests with 2APD and 2APDG is going on.
  • (this week we will have spectra with LED signals)
slide8

End November

meeting in Dubna

N

O

W

?

End of 2003

?

First

board

Prot. test

Materials ?

2 months

Pilot boards production

1 month

Second

board

HV test

If ok

LED calibr. Test?

APD V<400v generating on the board and tuning for each channel

APDG V<100v delivering on the board and tuning for each channel

slide9

Number of channels per board?

  • 4 FLC chips - 72 channels
  • ADC AD7924 12bit, 4 ch, 1µsec.
  • 100-150 µsec readout time
  • 2.LED test?
  • We need help for the mechanics design
  • VME modules?
  • We will need readout in February.
  • We can design and produce VME modules in time
  • 4 VME modules with TTC bus + VME controller.
  • Total cost for this solution 12k$.
  • Advantages:
  • Independence during customization (from ECAL)
  • Possibility of independent operation (from ECAL)
  • Faster DAQ
  • Complete system will be produced and tested before delivery
  • We need DAQ soon
slide10

HV

FLC

1

FLC

2

LVDS1

ADC

LVDS2

LVDS3

FLC

3

DAC

Charge

injection

FLC

4

LED

test