1 / 26

Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space

This presentation discusses a new approach to solving hard instances of FPGA routing, using a congestion-optimal restrained-norm path search space. The research goals include developing a range of FPGA routers for different designer constraints, which can save costs and improve FPGA architectures. The presentation outlines the problem of FPGA routing, prior approaches, the concept of negotiated congestion, and the use of lexicographical ordered pairs for path evaluation. Experimental evaluation on the FPGA Challenge architecture is also discussed.

rchinn
Download Presentation

Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space Keith So School of Computer Science and Engineering University of New South Wales, Australia ISPD2007

  2. Presentation Outline • Introduction to FPGA Routing • Brief Review of Prior Work • Observed Problems with Standard Negotiated Congestion Formulations • New Lexicographical Path Search Space and Associated Properties • Application to Wirelength-Driven Routing • Future Work • Conclusions

  3. Research Goals • Develop a range of FPGA routers for different designer constraints • Identify potential for improvements through the study of known best state-of-the-art routers • More robust FPGA routers can save unit costs and allow area improvement in future FPGA architectures

  4. FPGA Routing Problem • FPGA Components • Logic blocks • Wire segments • Wire switches • Problem: To find an assignment of resources to nets that • Satisfies required connectivity • Satisfies electrical design rules • (Plus optional designer constraints)

  5. Routing Resource Graph • Converts the FPGA architecture into a digraph • Pins, Logic Blocks, Wire Segments  Vertices • Switches  Edges • Problem translates to finding mutually vertex-disjoint trees that implement the connectivity of nets

  6. A Simple Example • Example Netlist • Net 1: s1->t1 • Net 2: s2->t2 • Net 3: s3->t2 and t3 • In practice, 1000s+ of nets and more complex graph

  7. Some Prior Approaches to FPGA Routing • Rip and reroute [Frankle92] • Global routing then detailed routing [Brown96,Lemieux97] • Transforms to SAT [Wood97,Nam99,Xu03] • Min-cost flow based[Lee03] • Negotiated Congestion based [Mcmurchie95,Betz97,Betz00,Fung03]

  8. Negotiated Congestion • Iterative route nets and gradually increase sharing penalty of overused resources • A* routing used to connect each net, with a cost function with congestion and secondary cost components • Sharing penalty cost is based on current congestion and congestion in previous iteration rounds and is monotonically increasing • Iterations continue until no electrical design rules are violated or until a maximum number of iterations reached (declares unroutability)

  9. NC on the Simple Example

  10. Typical Form for Negotiated Congestion Cost Functions • For vertex v: • occ(v): guard for congested vertex • p(v): present congestion cost, exponentially increasing • h(v): historical congestion cost • s(v): designer issued secondary cost • Path cost = sum of vertex costs

  11. Problems with Scalar Path Evaluation • In all previous implementations a weighted scalar projection is used for path evaluation • Optimality to the weighted functions has limited meaning to conditions in the terrain • Sometimes lead to suboptimal choices for congestion avoidance • Magnitude of congestion cost is exponentially increasing • Needed to ensure convergence • Will lead to numerical instability with floating point representations

  12. Suboptimal Choice with Respect to Congestion Cost • Suppose x is chosen by the A* router • Any path y on the Pareto line might have been chosen • Path z2 which is congestion free is not chosen • because it is not on the lower bound of candidate paths in the scalar function

  13. Phases in the Negotiated Congestion Cycle Phase 1 Phase 2

  14. Phases in the Negotiated Congestion Cycle Phase 3 Phase 4 Precision Lost!

  15. Solution: Lexicographical Ordered Pairs • Use a ordered pair to store congestion and secondary cost components • Pairwise addition: (c1,s1) + (c2,s2) = (c1+c2, s1+s2) • Define a dictionary order on elements: (c1,s1) < (c2,s2) if c1<s1 or [c1=s1 and c2<s2]

  16. Proof: Preservation of Admissibility • The OP transformation preserves admissiblity of scalar secondary heuristics • Proof: • Define f’(x)=(0,f(x)) for admissible f in scalar form • In OP space, the actual cost will be of the form (d,f(x)+e) • (0,f(x)) < (d,f(x)+e) for any nonnegative d and e so f’(x) is admissible in OP space • Shows that A* search will be optimal when using the OP comparator

  17. Properties of Searches in the Ordered Pair Space • Property 1: Path chosen will have minimum congestion cost • (w,x) < (y,z) if w < y • Property 2: If multiple paths of congestion cost x are available, path chosen will be the one with minimum secondary cost • (x,y) < (x,z) if y < z • Both properties handy for ensuring an “optimum choice” is made for each pin, assuming congestion cost measure “problem size’’

  18. Application: CornNC Wirelength Driven Router • Secondary cost is total wirelength • CornNC cost is an OP of congestion cost and expected wirelength to target: f(v)=(occ(v)c(v),WL(v)) • Congestion cost increased linearly per iteration, allows many iterations to be run (representation limit ~millions!)

  19. Experimental Evaluation • CornNC and VPR4.30 on the FPGA Challenge architecture and placements [Betz97] • Number of tracks parameterised to determine robustness • Runtimes and utilisation measured between mutually routable instances • Max iterations for CornNC = 1600

  20. Further Aspects for Investigation • Runtime Improvements • Congestion cost schedule refinement • Inclusion of multiple objectives • e.g. simultaneous power and timing/mintime-maxtime • Application to other domains • where negotiated congestion has been successfully applied

  21. Conclusions • Lexicographical ordered pair evaluation of candidate paths has useful properties and is numerically stable • Effective for solving difficult cases of wirelength FPGA routing with a significant (10%) improvement • Analytically promising for many other objectives because of provably desirable path choices

More Related