1 / 16

Overview and Status of ATLAS Pixel Detector

Overview and Status of ATLAS Pixel Detector. Waruna Fernando The Ohio State University on behalf of the ATLAS Pixel Collaboration. ATLAS Inner Detector. Electromagnetic Calorimeter. Solenoid. Endcap Toroid. Muon Detectors. TRT 420 K channels. SCT 6.2 M channels. Pixels

range
Download Presentation

Overview and Status of ATLAS Pixel Detector

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Overview and Status of ATLAS Pixel Detector Waruna Fernando The Ohio State University on behalf of the ATLAS Pixel Collaboration

  2. ATLAS Inner Detector Electromagnetic Calorimeter Solenoid Endcap Toroid Muon Detectors TRT 420 K channels SCT 6.2 M channels Pixels 80 M channels Inner detector Barrel Toroid Hadronic Calorimeter • 1.15 m radius, 7 m long • coverage to |η| ≤ 2.5 • inside 2 T magnetic field

  3. Beam pipe SQP’s Barrel EndCap Endcap SQP’s PP0 PP1 PP0 PP1 7m Pixel Package Overview • Detector (barrel+ 2 Endcaps) • SQPs (8 Services Quarter Panels) • Beam Pipe and Services Supports

  4. Pixel Sensor • p+ pixels on n substrate • Sensor bump bonded to 16 FE chips • 41,984 50 μm x 400 μm Pixels • Special pixels for chip overlap regions: • 5,248 “long” 50 μm x 600 μm • Ganged pixels ganged

  5. Pixel Front-End (FE) Chips 50x50m • Converts charge into Time over Threshold (ToT) • Buffering + time stamp logic • Charge injection • Detailed monitoring • 2,880 channels organized in 18 columns and 160 rows 11mm

  6. Pixel Module • 0.25 μm CMOS FE chips • connect to MCC • Zero suppression and first event building • Fast readout • (25 ns beam crossing, 3.2 μs latency) • Radiation hard to 50 MRad (NIEL > 1015 1 MeV neq/cm2) FE Chip Module Controller Chip (MCC) 2.2cm 6cm

  7. Pixel Detector Staves Barrel Endcap Disks Modules • 3 barrel layers, 2x3 disks • Total of 1,744 Modules • Good impact parameter resolution due to B-Layer at 5 cm

  8. Pixel Services PP1 PP0 Pixel Readout Control/Data Signals (Opto Links) Sensor MCC FE chips 2880 Type 0 fibers . . 16 chips . ~100m Cooling FE chips 2880 Power 4 fast +4 slow Service Panel Pixel Module

  9. Service Panels • 4 Service Quarter Panels (SQP) in each side • SQP to route services to the outside of the Inner Detector Volume • Module can send data with 40(L2), 80(L1, Disk) or 160(B) Mbit/s • Opto-board services 6/7 modules • 36 opto-boards per SQP

  10. VCSEL VDC DORIC VCSEL: Vertical Cavity Surface Emitting Laser diode VDC: VCSEL Driver Circuit PIN: Pin diode DORIC: Digital Optical Receiver Integrated Circuit PIN Opto-Boards • Converts optical to electrical signal and vice versa • Contains optical links, each serving a pixel module • B-layer : two data links per module due to high hit occupancy • L1, L2 and disks: one data link per module • Fabricated with BeO for heat management

  11. Temperature Dependent • Optical power of some VCSEL channels decreases rapidly@ low T • Characteristic of the VCSEL array • There is only one parameter to change optical power (VISET) and it is common to the entire array (in the B layer common to both arrays) • Known problem for long time • planned to run at 10 C • some locations were much cooler than anticipated Optical power (uW) 10C 5C -5C -10C -15C -20C -25C Channel

  12. Temperature Dependent (cont.) • Solution: install heaters heater Copper/Kapton blankets NTC

  13. CSR (Common Serial Resistance) • Symptom: like a dead VCSEL • Some “failed” boards recovered • How to identify those recovered? • A procedure is developed to measure the resistance of the inaccessible CSR and rejected the worst.(~7% ) • Still not understood the reason • conductive epoxy (5 μm) under the VCSEL array is thinner • than manufacturer's recommendation (15 μm) • After installation started in Oct 06, not a single board failed due to this. Voltage (V) CSR Current (mA) VCSEL

  14. Slow Turn On (STO) • Was first discovered in SCT, but we failed to find any in our test system • System test with prototype SQP found some STO • A new testing procedure added to identify the arrays with STO and rejected ~7%. • Depends on the distance from the VCSEL to fiber • Beveled finish on MT connector in system test allows fiber to be closer to VCSEL • Different modes of operation change with time ? • No board is found to have severe STO after installation

  15. Current Status • Connectivity test • Check the modules can be setup and read out through opto-boards • Summary of problems not resolved in the Connectivity test • One dead link due to a failed PIN channel (cold solder?) rerouted but practically hard to operate. • A short between power and clock in a module • HV wire broken in a cable that is not accessible • Short on one FE chip: module is working with 15 FE chips. • Only 4/1744 Modules defective (May be 2 are recoverable)

  16. Current Status (cont.) • Inserted the pixel package into the Dummy Support Tube (DST) and Installation at pit started. • Summer: installation of services in the pit. • Fall: Connectivity test in the pit followed by cosmic and collision data!!

More Related