1 / 7

Selection of Architectures for CMOS Mixed Signal IC Design: Focus on DAC

This presentation explores various architectures for Digital to Analog Converters (DACs) in CMOS mixed-signal IC design. We cover the Nyquist rate, oversampling, and different DAC types such as Binary Weighted, Thermometer Coded, Direct Encoded, Hybrid, and Algorithmic architectures. Each architecture's advantages and disadvantages are analyzed, highlighting aspects like speed, power consumption, circuit complexity, and matching difficulties. The presentation emphasizes the Double Segmented Thermometer Coded with Binary Weighted Current Steering architecture as a promising solution meeting SFDR and speed requirements.

raanan
Download Presentation

Selection of Architectures for CMOS Mixed Signal IC Design: Focus on DAC

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. EE5316 CMOS MIXED SIGNAL IC DESIGN – PRESENTATION 1 (SELECTION OF ARCHITECTURE)DIGITAL TO ANALOG CONVERTER - Rushabh Mehta, Manthan Sheth The University of Texas at Arlington

  2. ARCHITECTURE NYQUIST RATE OVERSAMPLING INTERPOLATING • BINARY WEIGHTED • Fast • Less complex circuitry • Prone to mismatch errors • THERMOMETER CODED • Easy matching • Monotonic • Better INL & DNL than binary weighted • Slower than binary weighted • DIRECT ENCODED • Low speed due to RC delays • Resistor matching difficult • HYBRID • Contains segments of various other architectures • ALGORITHMIC • Slow • High real estate & power consumption The University of Texas at Arlington

  3. BINARY WEIGHTED DAC • CURRENT STEERING • Consumes less real estate • Fast for resolution < 10bits • High power efficiency • R - 2R LADDER • High power consumption • Good impedance matching • Prone to glitch problems • CHARGE REDISTRIBUTION DAC • Slow due to RC delays • Finite bandwidth of opamp The University of Texas at Arlington

  4. THERMOMETER CODED DAC • Converts binary input into thermometer code • N binary inputs give 2n – 1 thermometer coded bits • Reference elements are equal in size thus aiding matching of the various elements • Monotonic in nature with INL & DNL better than binary weighted DACs The University of Texas at Arlington

  5. HYBRID DAC • Employs a combination of the afore-mentioned architectures • Hence includes the advantages of the respective architecture The University of Texas at Arlington

  6. DOUBLE SEGMENTED THERMOMETER CODED WITH BINARY WEIGHTED CURRENT STEERING • For the given specifications, the Double Segmented Thermometer Coded with Binary Weighted Current Steering hybrid architecture is used. • It promises to meet the required SFDR and Speed requirements. • Double segmented is proposed for reduced area 12 The University of Texas at Arlington

  7. CIRCUIT IMPLEMENTATION Current Steering implementation for Thermometer Coded DAC Segment Current Steering implementation for Binary Weighted DAC Segment The University of Texas at Arlington

More Related