What every Architect should know about Technology, Sani R. Nassif,

1. 3D-ICan Enabler Technology and a new LandscapeYves LeducAdvanced System Technology November 2009

2. Forewarning, our only concern: MANUFACTURABILITY: the ability to create PROFITABLE IC’s. What every Architect should know about Technology, Sani R. Nassif, IBM Research Austin.Design Variability: Challenges and Solutions at microarchitecture -architecture level DATE’08, München

3. Motivation • Glossary • Technology • Enabled Innovations • Status • New Jobs

4. 3D-SIP Motivations 3D-STV

5. According to SEMATECH http://www.sematech.org/research/3D/index.htm • The advantages of 3D-TSV over the alternatives • By combining the performance and power of system-on-chip (SOC) with the functionality and time-to-market advantages of system-in-package (SiP), TSV offers the best of both for achieving very high densities for memory and logic. Its advantages over SoC and SiP include: • Greater density for the same footprint • More functionality • Higher performance • Lower power consumption • Lower cost • More manufacturing flexibility • Faster time to market

6. y r x z y r x Larger the die, more appealing is 3D interconnect 2D Span of Control n  r2 3D Span of Control n  r3

7. Glossary

8. Pads dies interface Pads dies interface dies interface Glossary: F2F, B2F • F2F,where dies are soldered Face to Face • B2F, where dies are bonded Back to Face Microbumps Silicon Through Vias aka STV

9. Glossary: D2W, W2W • D2W,Die to WaferSoldering F2F • Bonding B2F • W2W,Wafer to WaferBonding B2F

10. F2F F2F B2F WSP Compatible Multi B2F 3D-IC’s

11. One Example of 3D-IC Technology B2F, D2W

12. Temporary carrier Temporary carrier bonding Processed wafer A, with STV Silicon of wafer A thinningDies singulation Temporaryadhesive coating Dies A to wafer B alignment Processed wafer B Adhesive coating Die bonding Super dies singulation Carrierremoval Super dies an Example from IMEC: 3D-IC[ Snapshot ]

13.  an Example from IMEC: 3D-IC Carrier Super-dies are singulated

14. Technical Dashboard • What is IMPORTANT to have? • The removal of the die to die ESD protections to get the density of STV without impacting the circuit integration. • Low pin count solution to make WSP possible. • Thermal awareness. • What will be the key ENABLER? • Wafer thinning technology drives directly cost and STV densities. • What -SEEM- to be the BEST technical options? • B2F, as bonding should be preferred to soldering for STV densities. • ? ‘Vias First’ STV brings highest density, but processed in wafer fab • ? ‘Vias Last’ STV are built in assembly plant • D2W or W2W: currently unclear.

15. Usage: System area System cost Performances Flexibility Heat dissipation PCB process complexity Package process complexity Risks Technology maturity WSP compatibility

16. Enabled Innovations

17. Die 3 >1000’s connections / mm2 One Super-Die Die 2 Die 1 3D-IC is a SOC Technology 3D-IC is a technology breaking the boundaries of IC’s. It offers direct connections between modules. The super-die created by the bonding of several dies is not an assembly of dies but a true SOC with superior connections.

18. 7 8 6 5 9 2 12 3 13 1 11 10 4 14 3D Topology brings more Compact Architecture Compared to 2D counterparts, 3D-IC SOC’s have shorter connections to many more neighbors. They offer many more connection planes and shorter paths to route signals.

19. Superior Connections without Penalty 1.2V – 3.0V Pads ESD protections I/O’s Low RLC connections No pad No ESD protection 1.2V There is no need to specific drivers to make die to die connections There is no need to place ESD protections on these internal connections

20. Example of Enhanced Performances SOC Low leakage 1.2V – 3.0V NOC SRAM cache 2 Embedded PM I/O’s … 1 000’s connections SRAM cache 1 DSP ARM … 1.2V • Massive transfer between cache memories breaks data transfer bottleneck. • Tuned processes offer lower cost and better performances. • Enhanced connection capability by enabling efficient NOC solutions.

21. 1.2V – 3.0V 1.2V Example of a Flexible Platform WiFi, Bluetooth, NFC.. USB, FireWire.. NOC.. Power Management.. … 1 000’s connections Processors 1 000’s connections Memory

22. Enabling Application: Memory! 8 identical IC’s 8 * Memory N bits = Memory N bytes

23. Our only concern: Manufacturability 

24. CW = (CF+CV+CY)/(TPT*Y*U) where: CW = Cost per wafer CF = Fixed cost CV = Variable cost CY = Cost due to yield loss TPT = Throughput Y = Composite Yield U = Utilization [ July 2009 ] According to “Today, fabs running iTSV can produce 3D-TSV devices at a total Cost of Ownership of less than $150usd per wafer. Improved synchronization between the unit processes along with aggressive cost saving designs have been very successful at exceeding the consortium’s original cost goals.” http://www.emc3d.org/documents/pressReleases/2009/EMC3D_consortium_continuation_July2009.pdf

25. KEY ENABLER Samsung debuts world’s thinnest multi-die package Samsung Electronics has developed the world’s thinnest multi-die package, one that measures 0.6mm in height. Designed initially for 32 gigabyte (GB) densities, the new memory package is just half the thickness of a conventional memory package of eight stacked chips (or dies). The advanced packaging technology delivers a 40 percent thinner and lighter memory solution for high-density multimedia handsets and other mobile devices, according to the company. […]   The newly developed ultra-thinning technology overcomes the conventional technology limits of a chip’s resistance to external pressure when under 30um in height. The productivity decline resulting from this thickness limitation had been directly attributable to a drop in production yields during mass production. […] The 15um-thickness represents a significant achievement as it can allow for double the density of previous multi-chip packages. The thinner die also dramatically reduces chip weight. In addition, the new package technology can be adapted to other existing MCPs, configured as system in packages (SiPs), or package on packages (PoPs). The breakthrough technique for 15um-and-under chip thicknesses will allow for the design of very high density solutions with the smallest of form factors – an extremely attractive prospect for the highly competitive mobile market. [ November 2009 ] http://www.electroiq.com/index/display/article-display/3608609647/articles/advanced-packaging/industry-news/2009/11/samsung-debuts_world.html

26. System [r]evolution New know-how !

27. The Job of IC Designers is Changing! • 3D-IC is bringing many new degrees of freedom. • Packaging becomes a key technology and impacts early decisions. • System partitioning is more important than ever. • Early analysis is essential. • Analysis must be done from PCB to Silicon. • Analyze systems at the highest level. • Job is too serious to not involve early technical specialists. • Need a Strong Expertise in System Exploration, What-If analysis: • -> Process Performances Understanding and Cost evaluation • -> Specification modeling and simulation • -> Transaction level modeling and simulation • -> High Level Mixed Signal modeling and simulation • -> Heterogeneous modeling and simulation • -> Thermal modeling and simulation • -> Advanced Packaging • …

28. Open for discussion !