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Integration

Integration. R. Michaels, May 23, 2013. Combine (integrate) detectors and electronics so that the physics program is satisfied. System-wide issues e.g. trigger requirement, DAQ, hall infrastructure, switchover between experiments. Physics Program of SoLID.

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Integration

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  1. Integration R. Michaels, May 23, 2013 • Combine (integrate) detectors and electronics so that the physics program is satisfied. • System-wide issuese.g. trigger requirement, DAQ, hall infrastructure, switchover between experiments.

  2. Physics Program of SoLID • Parity Violation DIS: Quark Axial charge, Charge Symmetry Violation … • Inclusive DIS • SoLID-Spin : Nucleon Spin, Tensor Charge, TMD, Quark OAM … • Semi-inclusive Deep Inelastic Scattering (SIDIS) • J/ψ: Nucleon Mass, Non-perturbative gluons • Exclusive Process SoLID Collaboration Meeting

  3. Requirements

  4. Requirements, cont.

  5. Requirements, cont.

  6. Example: Combined pi/e ratio from Cerenkov & Calorimeter for PVDIS as function of polar angle and momentum As shown last meeting and in PCDR This is “the best it can be”, but not a L1 or L3 trigger. Question: what are the L1 & L3 rates ? Goal: error in pion contamination < 10-3 0.02 % 0.2 % • Work done by • XinQian • Mike Paolone • Jin Huang 1.5 %

  7. DAQ Basics Frontend (e.g. FADC) L1 Crate processor Global Processing (SSP, GTP) Frontend (e.g. FADC) L3 Farm Other crates 8 usec pipeline Tape

  8. DAQ Basics FPGA FPGA Frontend (e.g. FADC) FPGA L1 Crate processor Global Processing (SSP, GTP) Frontend (e.g. FADC) L3 Farm Other crates FPGA FPGA – programming at each level of hardware. Tape flexibility

  9. DAQ Basics L1 < 100 Khz ? Frontend (e.g. FADC) L1 < 100 Khz ? (entire system) Crate processor Global Processing (SSP, GTP) Frontend (e.g. FADC) L3 Farm Other crates L3 < 300 MB/sec ? Q: What limits allowed at each stage ? Tape

  10. Bob Michaels, KalyanAllada, AlexandreCamsonne, and DAQ Group 12 GeV DAQ Test Stand –Initially for Compton Upgrade FADCCounting Mode Photon DAQ – present effort e-det (We have a prelim. spec. of a VXS-based pipelining trigger board to be prototyped in ~1 year for 7K$) hallaweb.jlab.org/equipment/daq/compton_coda3.pdf hallaweb.jlab.org/wiki/index.php/ComptonDaqDev

  11. 12 GeV DAQ Test Stand –Initially for Compton Upgrade An event in the FADC Setup(moved to TEDF)

  12. Trigger Simulation Studies to Be Performed (possibly) Goals:estimate L1 and L3 rates and efficiencies to “keep the physics”. Inform the trigger/DAQ design effort. Maybe something quick can be done using the software that combined “best possible” PID, i.e. put in rates and some crude model of trigger ??? Use existing Geant setups to define models for the response of detectors (amplitude distributions). GEMC generates events and tracks particles into detectors, where models are applied. The models are being specified Unify all the Geant efforts into one common framework. Encode rate effects , digitization by the DAQ, and trigger logic at L1 and L3. (perhaps best approach, but takes longest) YuxiangZhao, Yi Qiang, RakithaBeminiwattha, Michael Paolone, Jin Huang, Zhiwen Zhao

  13. Some Issues • We need hardware experience with 12 GeV DAQ technology • Work on combining detectors to design triggers • Calibrations -- see Rich’s talk (March 22) • and Xin’s talk (Dec 14) • What do we really need for the PCDR ?

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