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A Hardware Implementation of the Blowfish Cipher. Michael C.-J. Lin Youn-Long Lin Department of Computer Science Tsing Hua University Hsin-Chu, Taiwan 300, R.O.C. Outline. Introduction Blowfish Algorithm Hardware Architecture Hardware Requirement Conclusion.

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A hardware implementation of the blowfish cipher

A Hardware Implementation of the Blowfish Cipher

Michael C.-J. Lin Youn-Long Lin

Department of Computer Science

Tsing Hua University

Hsin-Chu, Taiwan 300, R.O.C


Outline
Outline Cipher

  • Introduction

  • Blowfish Algorithm

  • Hardware Architecture

  • Hardware Requirement

  • Conclusion


Introduction
Introduction Cipher

  • Blowfish Algorithm

    • Block cipher : 64-bit block

    • Variable key length : 32 ~ 448-bit key

    • Unpatented and royalty-free, no license required

  • Hardware Implementation

    • datapath : addition, xor ( 32-bit operand )

    • memory : 4K bytes


Blowfish algorithm
Blowfish Algorithm Cipher

  • Key expansion + Data encryption

  • Key expansion ( Initialization )

    • key expanded to P array and S box ( total 4148-byte )

    • P array ( P1 ~ P18 : each 32-bit )

    • S box array ( 4-box, each includes S0 ~ S255 , each 32-bit )

  • Data encryption

    • key permutation, key and data substitution

    • only add and xor operation, 32-bit operand


Key expansion

Step 1 : Cipher

1.expand key to 576-bit

2.xor with P array

3.store results of 2 in P array

Step 2 :

datal = 0x00000000;

datar = 0x00000000;

for (i = 0; i <= 16; i += 2) {

Blowfish_encipher(&datal, &datar);

bf_P[i] = datal;

bf_P[i + 1] = datar;

}

for (i = 0; i <= 3; ++i) {

for (j = 0; j <= 255; j += 2) {

Blowfish_encipher(&datal, &datar);

bf_S[i][j] = datal;

bf_S[i][j + 1] = datar;

}

}

Key expansion

Fig 1. Key Expansion


Data encryption
Data encryption Cipher

Fig 2. Data Encryption Flow


Function f
Function F Cipher

Fig 3. Function F


Hardware architecture
Hardware Architecture Cipher

Fig 4. Chip Specification

Table 1. Mode Spec.


Hardware architecture1
Hardware Architecture Cipher

Fig 5. Top Module


Hardware architecture2
Hardware Architecture Cipher

  • e1: Finish loading data from ROM to SRAM

  • e2: Finish initialization and mode != 1

  • e3: Finish encryption and mode != 2

  • e4: Finish decryption and mode != 3

Fig 6. FSM of Controller


Hardware architecture3
Hardware Architecture Cipher

Fig 8. Blowfish


Hardware architecture4
Hardware Architecture Cipher

Fig 7. Core


Hardware requirement
Hardware requirement Cipher

  • Memory

    • SRAM ( 4K bytes for S box ) : 8 mm2

  • ROM : 4K bytes

    • Random logic : 10K gates

    • ROM compiler : 2mm2

  • Blowfish : 12K gates

    • Datapath : 10K gates

    • Controller : 2K gates

  • Report area : Compass 0.6m cell library

  • Speed predict : 100 MHz


Conclusion
Conclusion Cipher

  • Key length is variable : 32 ~ 448-bit

  • Suitable application

    • Key doesn’t change often ( ex. Communication link )

  • Compact : only 4K bytes memory

  • Simple operation : addition, xor and table look-up