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241-440 Computer System Design Lecture 4. Wannarat Suntiamorntut. Part I : Single Data Path. Outline. Design a Processor step by step Requirement of instruction set Components and clocking Testing Datapath Control Datapath. Processor. Datapath. M E M O R Y. Input. Control.

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241 440 computer system design lecture 4

241-440Computer System DesignLecture 4

Wannarat Suntiamorntut

241-440 @ W.S.

outline
Outline
  • Design a Processor step by step
  • Requirement of instruction set
  • Components and clocking
  • Testing Datapath
  • Control Datapath

241-440 @ W.S.

five component of computer

Processor

Datapath

M

E

M

O

R

Y

Input

Control

Output

Five Component of Computer

241-440 @ W.S.

performance perspective
Performance Perspective
  • Performance of machine is determined by CPI
  • Processor Design :

clock cycle time

clock per instruction

  • Single cycle processor :

adv. : one clock cycle per instruction

disadv. : long cycle time

241-440 @ W.S.

design processor step by step
Design Processor Step by Step

1. Analyze instruction set ==> Datapath requirement

2. Selection Set of datapath and establish clocking methodology

3. Assembly datapath meeting requirement

4. Analyze implementation of each instruction to determine setting of control

5. Assembly the control logic

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step 1
Step 1
  • ADDU rd, rs, rt SUBU rd, rs, rt
  • ORI rt, rs, imm16

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step 11
Step 1
  • lw rt, rs ,imm16 sw rt, rs, imm16
  • beq rs, rt, imm16

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slide10
RTL
  • All instructions start by fetching

Mem[PC]

ADDU rd <= rs + rt; PC = PC + 4

SUBU rd <= rs + rt; PC = PC + 4

Ori rt <= rs + zero_ext(imm16);PC = PC + 4

LOAD rt <= mem[rs] + sign_ext(imm16); PC=PC + 4

STORE mem[rs] + sign_ext(imm16)<=rt; PC=PC+4

BEQ if rs = rt then PC=PC+sign_ext(imm16)||00

else PC = PC + 4

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step 1 the requirement from instruction
Step 1 : The requirement from instruction
  • Memory

Data & Instruction

  • Register (32 x 32)

Read rs Read rt Write rt or rd

  • PC
  • Extender
  • Add and sub register or extend immediate
  • Add 4 or extended immediate to PC

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step 2 components of datapath
Step 2 : Components of datapath
  • Combination Element
  • Storage elements

Clocking methodology

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combination elements
Combination Elements

Adder MUX

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combination elements1
Combination Elements

ALU

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storage element register
Storage Element : Register
  • Similar to D-flip/flop
  • Write enable

negated(0) : Data out

won’t change

asserted(1) : Data out

will be data in

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register file
Register file
  • Consist of 32 registers
  • Ra select register to bus A
  • Rb select register to bus B
  • Rw select register to be written via bus W

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storage ideal memory
Storage : Ideal Memory
  • One Input
  • One Output
  • Memory word is selected

by Address, Write enable = 1 then the

data will be written

  • Clock input : is a factor only during write operation
  • During read operation : behaves on combination logic.

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clock methodology
Clock Methodology

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step 3
Step 3 :
  • Register Transfer Requirements

--> Datapath Assembly

  • Instruction Fetch
  • Read Operands and Execute Operation

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step 3 a instruction fetch unit
Step 3 a : Instruction Fetch Unit

Update PC : Sequence Code: PC <= PC + 4

Branch and Jump : PC <- something else

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step 3b add sub
Step 3b : Add & Sub

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step 3f branch instruction
Step 3f: Branch instruction

beq rs, rt, imme16

  • mem[pc]
  • equal <= rs = rt
  • if (con eq 0) then PC<=PC+4+(signExt(imm16)x4);

else PC <= PC + 4;

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put it all together
Put it all together

241-440 @ W.S.

step 4 control path
Step 4 : Control Path

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meaning of control signal
Meaning of control signal
  • Rs, Rt and Imme16 hardwire to datapath
  • nPC_sel : 0 => PC
  • PC<= PC+4, 1 => PC
  • PC <= PC + 4 +

signExt(Imm16) || 00

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meaning of control signals
Meaning of control signals

ExtOp : Zero, sign MemWr:write memory

ALUsrc: 0=>regB, 1=>imme Memtoreg:1=>mem

ALUcrt : add, sub, or ReqWr : write dest. Reg.

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control signals
Control Signals

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example load flow
Example : Load Flow

241-440 @ W.S.

next on lecture 5
Next on Lecture 5

241-440 @ W.S.