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Pay Me Now or Pay Me Later Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model Design. Paul Graykowski Senior Staff CAE Synopsys. Andrew Piziali Independent Consultant. Agenda. Introduction Related Work The Design Under Verification

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slide1

Pay Me Now or Pay Me LaterExploring the Implementation and Analysis Cost Trade-Offs of Coverage Model Design

Paul Graykowski

Senior Staff CAE

Synopsys

Andrew Piziali

Independent Consultant

agenda
Agenda
  • Introduction
  • Related Work
  • The Design Under Verification
  • High-Fidelity Coverage Model Design
  • Coverage Data Analysis
  • Summary

<Paul Graykowski> < Andy Piziali>

agenda1
Agenda
  • Introduction
  • Related Work
  • The Design Under Verification
  • High-Fidelity Coverage Model Design
  • Coverage Data Analysis
  • Summary

<Paul Graykowski> < Andy Piziali>

introduction
Introduction
  • Challenge in balancing the conflicting requirements of coverage model fidelity
    • Fidelity – how closely the model reflects the behavioral space of the feature
      • Number of attributes
      • Model structure precision
    • Model size – number of points defining the model
    • Counter-intuitive relationship
      • Increasing fidelity decreases model size
      • Decreasing fidelity increases model size

<Paul Graykowski> < Andy Piziali>

introduction1
Introduction
  • Low fidelity coverage model
    • Less design and implementation time
    • More data analysis time
    • More storage required for coverage data
  • High fidelity coverage model
    • More design and implementation time
    • Much less data analysis time
    • Less storage required for coverage data

<Paul Graykowski> < Andy Piziali>

agenda2
Agenda
  • Introduction
  • Related Work
  • The Design Under Verification
  • High-Fidelity Coverage Model Design
  • Coverage Data Analysis
  • Summary

<Paul Graykowski> < Andy Piziali>

related work
Related Work
  • “I'm Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor”
  • “User Defined Coverage — A Tool Supported Methodology for Design Verification”
  • “OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification”
  • “Hole Analysis for Functional Coverage Data”
  • Functional Verification Coverage Measurement and Analysis
  • ESL Design and Verification

<Paul Graykowski> < Andy Piziali>

agenda3
Agenda
  • Introduction
  • Related Work
  • The Design Under Verification
  • High-Fidelity Coverage Model Design
  • Coverage Data Analysis
  • Summary

<Paul Graykowski> < Andy Piziali>

the design under verification
The Design Under Verification
  • OpenCores.org WISHBONE DMA controller
  • Transfers data between two WISHBONE interfaces
  • Provides interface bridge for direct slave access
  • Controller features:
    • Up to 31 DMA channels
    • 2, 4 or 8 priority levels
    • Linked list descriptors support
    • Circular buffer support
    • FIFO buffer support
    • Hardware handshake support

<Paul Graykowski> < Andy Piziali>

agenda4
Agenda
  • Introduction
  • Related Work
  • The Design Under Verification
  • High-Fidelity Coverage Model Design
  • Coverage Data Analysis
  • Summary

<Paul Graykowski> < Andy Piziali>

high fidelity coverage model design
High-Fidelity Coverage Model Design
  • What is a high-fidelity coverage model?
  • Top level design
  • Detailed design
  • Implementation
  • Trade-offs

<Paul Graykowski> < Andy Piziali>

what is a high fidelity coverage model
What is a High-Fidelity Coverage Model?
  • A model that precisely reflects the behavior of its associated feature

DMA Transfer

Transfer Kind

READ WRITE

BLK_RD BLK_WR

RMW

Transfer Address

0000_0004 FFFF_FFF8

0000_0000

FFFF_FFFC

0000_0004 7FFF_FFF8

0000_0000

7FFF_FFFC

8000_0004 FFFF_FFF8

8000_0000

FFFF_FFFC

<Paul Graykowski> < Andy Piziali>

coverage model top level design
Coverage Model Top-Level Design

Record all DMA transfer kinds for each address space.

  • Semantic description
  • Model attributes
    • DMA transfer kind
    • DMA transfer address
  • Attribute values
    • Transfer kind: READ, WRITE, BLK_RD, BLK_WR, RMW
    • Address: 0000_0000...FFFF_FFFC
  • Model structure
    • Matrix
    • Hierarchical
    • Structural hybrid

<Paul Graykowski> < Andy Piziali>

coverage model top level design1
Coverage Model Top-Level Design

Record each DMA transfer kind with its corresponding address space.

  • Semantic description
  • Model attributes
    • DMA transfer kind
    • DMA transfer address
  • Attribute values
    • Transfer kind: READ, WRITE, BLK_RD, BLK_WR, RMW
    • Address: 0000_0000...FFFF_FFFC
  • Model structure
    • Matrix
    • Hierarchical
    • Structural hybrid

<Paul Graykowski> < Andy Piziali>

coverage model top level design2
Coverage Model Top-Level Design
  • Three questions must be answered:
    • What must be sampled for the attribute values?
    • Where in the verification environment should we sample?
    • When should the data be sampled and correlated?
  • Verification environment
    • SystemVerilog and VMM
    • Class wb_cycle is a WISHBONE transaction
    • wb_cycle instance named cycle
    • cycle.kind and cycle.addr

<Paul Graykowski> < Andy Piziali>

coverage model detailed design
Coverage Model Detailed Design
  • What must be sampled for the attribute values?
    • cycle.kind and cycle.addr
    • Arranged as a matrix structure
  • Where in the verification environment should we sample?
    • Class wb_master_cb_cov extends wb_master_callbacks
  • When should the data be sampled and correlated?
    • Sample and correlate at transaction completion: wb_master_callbacks.post_cycle()

<Paul Graykowski> < Andy Piziali>

coverage model implementation
Coverage Model Implementation

class wb_master_cb_cov extends wb_master_callbacks;

wb_cycle cycle;

covergroupmaster_cov;

option.per_instance = 1;

c_kind: coverpointcycle.kind {

bins s_READ = {wb_cycle::READ};

bins s_WRITE = {wb_cycle::WRITE};

bins s_BLK_RD = {wb_cycle::BLK_RD};

bins s_BLK_WR = {wb_cycle::BLK_WR};

bins s_BLK_RMW = {wb_cycle::RMW};

}

addr: coverpointcycle.addr[31:0] {

bins s_LO_00 = {[32’h0000_0000]};

bins s_LO_04 = {[32’h0000_0004]};

bins s_MID = {[32’h0000_0008:

32’hFFFF_FFF4]};

bins s_HI_F8 = {[32’hFFFF_FFF8]};

bins s_HI_FC = {[32’hFFFF_FFFC]};

}

rwXaddr: cross c_kind, addr;

endgroup

extern function new();

extern virtual task post_cycle(

wb_masterxactor, wb_cycle cycle); ...

endclass:wb_master_cb_cov

task post_cycle(wb_master

cycle, wb_cycle cycle);

// Downcast from vmm_data

// to wb_cycle

$cast(this.cycle, cycle);

// Manually trigger a

// coverage update with

// the current wb_cycle

master_cov.sample();

endtask:post_cycle

<Paul Graykowski> < Andy Piziali>

coverage model design trade offs
Coverage Model Design Trade-Offs
  • Low-fidelity model
    • Less labor to design and implement 1 unit reference
    • Much more labor required for analysis 1 unit reference
    • Model is larger, requiring more storage 1 unit reference
  • High-fidelity model
    • More labor to design and implement 2.5x lo-fi model
    • Much less labor required for analysis 0-10% of lo-fi model
    • Model is smaller, requiring less storage ¼ – ⅓ lo-fi model

<Paul Graykowski> < Andy Piziali>

high fidelity coverage model implementation
High-Fidelity Coverage Model Implementation

addr: coverpointcycle.addr[32:0] {

bins s_rw_lo = {0} iff

(cycle.kind==wb_cycle::READ ||

cycle.kind==wb_cycle::WRITE);

bins s_rw_mid = {[32'h0000_0004:

32'hFFFF_FFF8]} iff

(cycle.kind==wb_cycle::READ ||

cycle.kind==wb_cycle::WRITE);

bins s_rw_hi = {32'hFFFF_FFFC} iff

(cycle.kind==wb_cycle::READ ||

cycle.kind==wb_cycle::WRITE);

bins s_blk_lo = {32'h0000_0000} iff

(cycle.kind==wb_cycle::BLK_RD ||

cycle.kind==wb_cycle::BLK_WR);

...

bins s_rmw_lo = {32'h8000_0000} iff

(cycle.kind==wb_cycle::RMW);

bins s_rmw_mid = {[32'h8000_0004:

32'hFFFF_FFF8]} iff

(cycle.kind==wb_cycle::RMW);

bins s_rmw_hi = {32'hFFFF_FFFC} iff

(cycle.kind==wb_cycle::RMW);

}

rwXaddr: cross c_kind, addr {

option.cross_auto_bin_max = 0;

bins s_cross_rlo = binsof(c_kind)

intersect {wb_cycle::READ} &&

binsof(addr.s_rw_lo);

bins s_cross_rmd = binsof(c_kind)

intersect {wb_cycle::READ} &&

binsof(addr.s_rw_mid);

bins s_cross_rhi = binsof(c_kind)

intersect {wb_cycle::READ} &&

binsof(addr.s_rw_hi);

...

bins s_cross_bkrlo = binsof(c_kind)

intersect {wb_cycle::BLK_RD} &&

binsof(addr.s_blk_lo);

...

bins s_cross_rmwlo = binsof(c_kind)

intersect {wb_cycle::RMW} &&

binsof(addr.s_rmw_lo);

...

bins s_cross_rmwhi = binsof(c_kind)

intersect {wb_cycle::RMW} &&

binsof(addr.s_rmw_hi);

}

<Paul Graykowski> < Andy Piziali>

agenda5
Agenda
  • Introduction
  • Related Work
  • The Design Under Verification
  • High-Fidelity Coverage Model Design
  • Coverage Data Analysis
  • Summary

<Paul Graykowski> < Andy Piziali>

coverage data analysis
Coverage Data Analysis
  • Hole aggregation
  • Hole partitioning
  • Hole projection

Valid Coverage Point

Invalid coverage point

<Paul Graykowski> < Andy Piziali>

hole aggregation
Hole Aggregation
  • Coverage holes with common attribute values are coalesced into a single region
  • Aggregate hole <RMW, {8000_0000, FFFF_FFFC}>

Filled coverage point

Coverage Hole

<Paul Graykowski> < Andy Piziali>

hole partitioning
Hole Partitioning
  • Block and atomic transfers to end regions prohibited
  • Coverage holes that are semantically similar are coalesced into a single region
  • <{{BLK_RD,BLK_WR}, 0000_0000}, {RMW, FFFF_FFFC}>

<Paul Graykowski> < Andy Piziali>

hole projection
Hole Projection
  • Collapse one or more dimensions of the model
  • Projected hole <*: {0000_0000, FFFF_FFFC}>

<Paul Graykowski> < Andy Piziali>

agenda6
Agenda
  • Introduction
  • Related Work
  • The Design Under Verification
  • High-Fidelity Coverage Model Design
  • Coverage Data Analysis
  • Summary

<Paul Graykowski> < Andy Piziali>

summary
Summary
  • Use high- and low-fidelity coverage models
  • Choose high- vs. low-fidelity coverage model trade-offs
  • Design process: top-level, detailed and implementation
  • Use the coverage model design table
  • Analyze using aggregation, partitioning and projection
  • Closing quote: “If you aren't using coverage, you should be taken out and beaten.” — Eric Hennenhoefer, verification methodology presentation

<Paul Graykowski> < Andy Piziali>

reference books
Reference Books

<Paul Graykowski> < Andy Piziali>