Course Review

1. 14 Course Review Kai Bu kaibu@zju.edu.cn http://list.zju.edu.cn/kaibu/comparch2017

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5. Lectures 02-03 Fundamentals of Computer Design

6. Classes of Parallel Architectures according to the parallelism in the instruction and data streams called for by the instructions: SISD, SIMD, MISD, MIMD

7. SISD • Single instruction stream single data stream • uniprocessor • Can exploit instruction-level parallelism

8. SIMD • Single instruction stream multiple data stream • The same instruction is executed by multiple processors using different data streams. • Exploits data-level parallelism • Data memory for each processor; whereas a single instruction memory and control processor.

9. MISD • Multiple instruction streams single data stream • No commercial multiprocessor of this type yet

10. MIMD • Multiple instruction streams multiple data streams • Each processor fetches its own instructions and operates on its own data. • Exploits task-level parallelism

11. Instruction Set Architecture ISA • actual programmer-visible instruction set • the boundary between software and hardware

12. ISA: Class • Most are general-purpose register architectures with operands of either registers or memory locations • Two popular versions register-memory ISA: e.g., 80x86 many instructions can access memory load-store ISA: e.g., ARM, MIPS only load or store instructions can access memory

13. ISA: Memory Addressing • Byte addressing supports accessing individual bytes of data rather than only larger units called words • Aligned address object width: s bytes address: A aligned if A mod s = 0

14. Each misaligned object requires two memory accesses

15. ISA: Addressing Modes • Specify the address of a memory object • Register Add R2, R1; R2<-R2+R1 • Immediate Add R2, #3; R2<-R2+3 • Displacement Add R2, 100(R1); R2<-R2+M[100+R1]

16. Trends in Cost • Cost of an Integrated Circuit wafer for test; chopped into dies for packaging

17. Trends in Cost • Cost of an Integrated Circuit percentage of manufactured devices that survives the testing procedure

18. Trends in Cost • Cost of an Integrated Circuit

19. Trends in Cost • Cost of an Integrated Circuit

20. Trends in Cost • Cost of an Integrated Circuit • N: process-complexity factor for measuring manufacturing difficulty

21. Dependability • Two measures of dependability Module reliability Module availability

22. Dependability • Two measures of dependability Module reliability continuous service accomplishment from a reference initial instant MTTF: mean time to failure MTTR: mean time to repair MTBF: mean time between failures MTBF = MTTF + MTTR 1st f 2nd f

23. Dependability • Two measures of dependability Module reliability FIT: failures in time failures per billion hours MTTF of 1,000,000 hours = 109/106 = 1000 FIT

24. Dependability • Two measures of dependability Module availability

25. Measuring Performance • Execution time the time between the start and the completion of an event • Throughput the total amount of work done in a given time

26. Measuring Performance • Computer X and Computer Y • X is n times faster than Y

27. Quantitative Principles • Parallelism • Locality temporal locality: recently accessed items are likely to be accessed in the near future; spatial locality: items whose addresses are near one another tend to be referenced close together in time

28. Quantitative Principles • Amdahl’s Law

29. Quantitative Principles • Amdahl’s Law: two factors 1. Fractionenhanced: e.g., 20/60 if 20 seconds out of a 60-second program to enhance 2. Speedupenhanced: e.g., 5/2 if enhanced to 2 seconds while originally 5 seconds

31. Quantitative Principles • The Processor Performance Equation

32. ICi: the number of times instruction i is executed in a program CPIi: the average number of clocks per instruction for instruction i

34. Lecture 04 Instruction Set Principles

35. ISA Classification • Classification Basis the type of internal storage: stack accumulator register • ISA Classes: stack architecture accumulator architecture general-purpose register architecture (GPR)

36. ISA Classes:Stack Architecture • implicit operands on the Top Of the Stack • C = A + B Push A Push B Add Pop C First operand removed from stack Second op replaced by the result memory

37. ISA Classes:Accumulator Architecture • one implicit operand: the accumulator one explicit operand: mem location • C = A + B Load A Add B Store C accumulator is both an implicit input operand and a result memory

38. ISA Classes:General-Purpose Register Arch • Only explicit operands registers memory locations • Operand access: direct memory access loaded into temporary storage first

39. ISA Classes:General-Purpose Register Arch Two Classes: • register-memory architecture any instruction can access memory • load-store architecture only load and store instructions can access memory

40. ISA Classes:General-Purpose Register Arch Two Classes: • register-memory architecture any instruction can access mem • C = A + B Load R1, A Add R3, R1, B Store R3, C

41. ISA Classes:General-Purpose Register Arch Two Classes: • load-store architecture only load and store instructions can access memory • C = A + B Load R1, A Load R2, B Add R3, R1, R2 Store R3, C

42. GPR Classification • ALU instruction has 2 or 3 operands? 2 = 1 result&source op + 1 source op 3 = 1 result op + 2 source op • ALU instruction has 0, 1, 2, or 3 operands of memory address?

43. Addressing Modes • How instructions specify addresses of objects to access • Types constant register memory location – effective address

46. Lectures 05-07 Pipelining

47. Pipelining start executing one instruction before completing the previous one

48. Pipelined Laundry 3.5 Hours Time Observations • No speed up for individual task; e.g., A still takes 30+40+20=90 • But speed up for average task execution time; e.g., 3.5*60/4=52.5 < 30+40+20=90 30 40 40 40 40 20 A Task Order B C D

49. MIPS Instruction • at most 5 clock cycles per instruction • IF ID EX MEM WB

50. MIPS Instruction IF ID EX MEM WB IR ← Mem[PC]; NPC ← PC + 4;