Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set

1. Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja,Rutgers University Tezaswi@caip.rutgers.edu Vishwani D. Agrawal, Agere Systems va@agere.com http://cm.bell-labs.com/cm/cs/who/va Michael L. Bushnell, Rutgers University bushnell@caip.rutgers.edu Bangalore, August 31, 2002 VDAT'02: Low-Power Design

2. Problem Statement • Design a digital circuit for minimum transient energy consumption by eliminating hazards VDAT'02: Low-Power Design

3. Theorem 1 • For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition Ref: Agrawal, et al., Proc. VLSI Design’99 VDAT'02: Low-Power Design

4. Theorem 2 • Given that events occur at the input of a gate (inertial delay = d ) at times t1 < . . . < tn , the number of events at the gate output cannot exceed tn – t1 -------- d min ( n , 1 + ) tn - t1 + d time t1 t2 t3 tn tn + d VDAT'02: Low-Power Design

5. Minimum Transient Design • Minimum transient energy condition for a Boolean gate: | ti - tj | < d Where ti and tj are arrival times of input events and d is the inertial delay of gate VDAT'02: Low-Power Design

6. Linear Program (LP) • Variables: gate and buffer delays • Objective: minimize number of buffers • Subject to: overall circuit delay • Subject to: minimum transient condition for multi-input gates • AMPL, MINOS 5.5 (Fourer, Gay and Kernighan) VDAT'02: Low-Power Design

7. Limitations of This LP • Constraints are written by path enumeration. • Since number of paths in a circuit is exponential in circuit size, the formulation is infeasible for large circuits. • Example: c880 has 6.96M constraints. VDAT'02: Low-Power Design

8. A New LP Model • Introduce two new variables per gate output: • ti Earliest time of signal transition at gate i. • Ti Latest time of signal transition at gate i. t1, T1 ti, Ti . . . tn, Tn VDAT'02: Low-Power Design

9. New Linear Program • Gate variables d4..d12 • Buffer Variables d15..d29 • Corresponding window variables t4..t29 and T4..T29. VDAT'02: Low-Power Design

10. Multiple-Input Gate Constraints For Gate 7: T7> T5 + d7; t7 < t5 + d7; d7> T7 - t7; T7> T6 + d7; t7 < t6 + d7; VDAT'02: Low-Power Design

11. Single-Input Gate Constraints Buffer 19: T16 + d19 = T19 ; t16 + d19 = t19 ; VDAT'02: Low-Power Design

12. Overall Delay Constraints T11<maxdelay T12<maxdelay VDAT'02: Low-Power Design

13. Validation of the Model For Gate 6 (path-enumeration model): d1 + d3 – d2< d6 d2 – d3 – d1< d6 VDAT'02: Low-Power Design

14. Validation of the Model For Gate 6 (new model): T6> T2 + d6; t6< t2 + d6; d6> T6 - t6; T6> T3 + d6; t6< t3 + d6; .. (Ineq. set A) VDAT'02: Low-Power Design

15. Validation of the Model Buffer Constraints: T2 = t2 = d2 ; T3 = t3 = d3 ; (Ineq. set B) Substituting Ineq. set B in Ineq. set A t6 – d2< d6 ..( 1 ) t6 – d1 – d3 < d6 ..( 2 ) d6 < T6 – d2 ..( 3 ) d6< T6 – d1 – d3 ..( 4 ) VDAT'02: Low-Power Design

16. Validation of New Model Adding ineq. ( 1 ) and ( 4 ), and using (A) d1 + d3 – d2< T6 – t6 <d6 Adding ineq. ( 2 ) and ( 3 ), and using (A) d2 – d3 – d1< T6 – t6 <d6 • These are the same inequalities as for the old path-enumeration model. • Similar derivation can be done for maxdelay constraints. • Hence the new model constraints are equivalent to the old ones. VDAT'02: Low-Power Design

17. Why New Model is Superior? • Path constraints from old model 4 × 4 × …4 = 4n • Constraints from new model 15 × n = 15n • Hence new constraint set is linear in size of circuit. VDAT'02: Low-Power Design

18. Comparison of Constraints 6.96x106 Number of constraints 3,611 c880 Number of gates in circuit VDAT'02: Low-Power Design

19. Results: Procedure Outline Combinational circuit netlist C++ Program Constraint-set AMPL* Optimized delays Power Estimator Results *Fourer, Gay and Kernighan, AMPL: A Modeling Language for Mathematical Programming, 1993. VDAT'02: Low-Power Design

20. Results: 1-Bit Adder VDAT'02: Low-Power Design

21. Estimation of Power • Circuit is simulated by an event-driven simulator for both optimized and un-optimized gate delays. • All transitions at a gate are counted as Events[gate]. • Power consumed  Events[gate] x # of fanouts. • Reference: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ISLPED`97). VDAT'02: Low-Power Design

22. Original 1-Bit Adder Color codes for number of transitions VDAT'02: Low-Power Design

23. Optimized 1-Bit Adder Color codes for number of transitions VDAT'02: Low-Power Design

24. Results: 1-Bit Adder • Simulated over all possible vector transitions • Average power = optimized/unit delay = 244 / 308 = 0.792 • Peak power = optimized/unit delay = 6 / 10 = 0.60 Power Savings : Peak = 40 % Average = 21 % VDAT'02: Low-Power Design

25. Results: 4-Bit ALU Power Savings : Peak = 33 %, Average = 21 % VDAT'02: Low-Power Design

26. Power Dissipation of ALU4 1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random vectors simulated in Spice 7 6 5 Original ALU delay ~ 3.5ns 4 Energy in nanojoules 3 Minimum energy ALU delay ~ 10ns 2 1 0 1.5 0.0 0.5 2.0 1.0 microseconds VDAT'02: Low-Power Design

27. Benchmark Circuits Circuit C432 C880 C6288 c7552 Maxdel. (gates) 17 34 24 48 47 94 43 86 Normalized Power No. of Buffers 95 66 62 34 294 120 366 111 Average 0.72 0.62 0.68 0.68 0.40 0.36 0.38 0.36 Peak 0.67 0.60 0.54 0.52 0.36 0.34 0.34 0.32 VDAT'02: Low-Power Design

28. Conclusion • Obtained an LP constraint-set that is linear in the size of the circuit. LP solution: • Eliminates glitches at all gate outputs, • Holds I/O delay within specification, and • Combines path-balancing and hazard-filtering to minimize the number of delay buffers. • New LP produces results exactly identical to old LP requiring exponential constraint-set. • Results show peak power savings up to 40% and average power savings up to 21%. VDAT'02: Low-Power Design