GAUT: Génération Automatic d’Unité de Traitement

1. GAUT: Génération Automatic d’Unité de Traitement ECE 667Fall 2014Synthesis and Verificationof Digital Circuits

2. Design flow for DSP applications • High-level Model • (C, Matlab) • High-Level Synthesis • RTL Model Logic Synthesis • Structural Netlist • (Gate-Level) Physical Synthesis • Physical Layout • Fabrication

3. Introduction • Due to rising complexity of modern digital circuits, a growing demand has emerged to design hardware at higher levels of abstraction targeting faster design adjustments and higher simulation speed. • To automate the design of such embedded systems, developing high-level synthesis tools that automatically convert the high-level specification to a lower level model (i.e. RTL, Structural Netlist (gate-level)) is desirable.

4. GAUT high-level synthesis tool • GAUT is a HLS (High Level Synthesis) tool developed at the Universite de Bretagne Sud (UB). Lab-STICC laboratory. • GAUT generates RTL descriptions from a pure bit-accurate algorithmic specification described in C/C++ language.

5. Design flow, where is GAUT? • High-Level Synthesis • with GAUT • C or C++ • Design Compiler by • Synopsys • XST(deliverd within • ISE) by Xilinx • QuartusII by Altera • … Logic Synthesis GAUT is compatible with XST for logic synthesis and Placement-& Rout ISE for physical synthesis Physical Synthesis • ASIC or FPGA

6. Interface • Inputs • A C or C++ file containing the algorithm to be synthesized. • A library of operators characterized for a given technology target • Outputs • A VHDL RTL code (.vhd file) • A description of the timing diagram of the I/O of the cicuit (.mem file) • Other files generated to interface GAUT with other tools for synthesis.

7. Architecture • The architecture of the hardware components that GAUT generates is composed of three main functional units: • Processing unit (PU) • Memory unit (MEMU) • Communication & Interface Unit (COMU)

8. GAUT target architecture

9. GAUT high-level synthesis flow Front End Back End

10. The Front End • The input description is a C/C++ function. • Algorithmic CTM class library from Mentor Graphics is used. This allows the designer to specify signed and unsigned bit-accurate integer and fixed-point variables by using ac_int and ac_fixed data types. • This library provides fixed-point data-types that supply all the arithmetic operations and built-in quantization (rounding, truncation. . . ) and overflow (saturation, wrap-around. . . ) functionalities.

11. The Front End • Example: ac_fixed <5,2,true,AC_RND,AC_SAT> is a signed fixed-point number of the form bb.bbb (five bits of width, two bits integer) for which the quantization and overflow modes are respectively set to ‘rounding’ and ‘saturation’.

12. The Front End • A) Compilation : • The role of the compiler is to transform the initial C/C++ specification into a formal representation which exhibits the data dependencies between operations. • The compiler of GAUT derives gcc/g++ 4.2 to extract a data flow graph (DFG) representation of the application. • The source file is processed in four main steps by gcc/g++: • 1) The C preprocessor (cpp) expands the preprocessor directives.

13. The Front End • 2) Constructs the Abstract Syntax Tree (AST) for each function of the source file. The AST tree is next converted into a CDFG like unified form called GENERIC. The GENERIC representation is lowered into a subset called GIMPLE form. • 3) False data dependencies are eliminated with Static Signal Assignment (SSA) and various scalar optimizations (dead code elimination, value range propagation, redundancy elimination). Loop optimizations (loop invariant, loop peeling, loop fusion, partial loop unrolling) are applied. • 4) The GIMPLE form is translated into the GAUT internal representation.

14. C code of Taylor(ex) GIMPLE form

15. The Front End • B) Bit-Width Analysis • Constant bit-width definition • Bit-width and value range propagation • C) Library Characterization • Library characterization uses a DFG, a technological library and a target technology. This step, based on commercial logic synthesis tools like ISE from Xilinx and Quartus from Altera, produces a library of time characterized operators to be used during the following HLS steps.

16. The Front End • D) Operation Clustering • Combine the computational function and the operation delay. This allows to indirectly consider operation’s bit-width since the propagation time of an operator depends on its operand’s size

17. GAUT Main Window

18. GAUT Main Window • The main window consists of the following design steps: • Compilation and graph exploration, • Library characterizing, • Datapathsynthesis, • Memory synthesis, • Communication & interface synthesis, • GANTT chart visualization, • Functional validation / simulation.

19. Step 1: Compiling the C code • Click on the yellow box with label of "C/C++ compiler". • Click on the open icon and select the path of the C/C++ file in your computer. For example C:\GAUT_2_4_3\test\taylorexp\taylorexp.c • Compile the code by clicking on the "compile button". IF there is any error in your code, gcc returns the errors. • Click on the graph tab and then click on the open button and load the taylorexp.cdfg file, which is the cdfg of the design. • "notech_16b“ is selected by default as the technological target library.

20. C/C++ Compiler Open Compile

21. Graph Tab Back to Flow

22. Graph Tab • The cdfg contains 3 additions, 2 multiplicatins, a division and a shif right operator. Data values stored in variables x, fact, powx, temp and some other variables that came from loop unrolling of the code. • Click on the "Back to Flow" button to back to the main window.

23. Step 2: Processing Unit Synthesis • The design of the Processing Unit (PU) integrates the following tasks: resource selection and allocation, operation scheduling, and binding of operations onto operators. • Click on the purple box with label of "VHDL Synthesis". • This part takes the cdfg generated in the previous step as the input. In the "Configuration" part in front of the "Graph" select taylorexp.cdfg file.

24. Processing Unit Synthesis

25. Step 2: Processing Unit Synthesis • Cadency: is the rate of arrival of the sets of data inputs (sampling rate, iteration interval, throughput). Cadency must be a multiple of the system clock period. • Clock: is the desired clock period of the future generated RTL component. • Memory constraint: select this box if you want to synthesize by using the memory mapping constraints if you plan to generate a Memory Unit. To do that, you need to fill the Memory Constraints tab.

26. Step 2: Processing Unit Synthesis • IO constraints: select this box if you want to synthesize by using I/O constraint. To do that, you need to fill the Input/Output Constraints tab. • Allocation strategy: you can choose between several allocation techniques listed in the first box. Using the second box you can choose between manual or automatic allocation. If you select manual, you can manually change the number of resources of each type.

27. Manual Allocation

28. Step 2: Processing Unit Synthesis • Scheduling strategy: you can choose between several scheduling algorithms (i.e., default, ASAP, no_pipeline, no_more_stage algorithms). • Vhdloutput: you can choos between different styles of VHDL codes. • Output: select Vhdl box to generate a .vhd RTL file, select the Gantt to obtain the .gantt file, select Mem box to generate a .mem file intended for Memory units and testbenchs. • Click on the Run button to start the synthesis.

29. Synthesis report

30. Synthesis report • CDFG parsing step • Number of nodes of cdfg • Time used for parsing cdfg • Selection step • Area • Time used for selection • Allocation step • Operators • CDFG latency • Time used for allocation

31. Synthesis report You can also see the active time of each operator on the Gantt chart • Scheduling step • Number of operators, latency, stages • Area of functional units • Usage rate of each operator ( active time of operator/ latency) • Time used for scheduling • Registers allocation step • Number of hardwired constants which are not stored in registers. • Number of fifo registers • Number of registers • Number of flip flop • Number of Multiplexer 2 to 1 • Time used for register allocation

32. Synthesis report • .mem generation • Number of pipeline stages • Time used for .mem generation • .vhd generation • Time used for .vhd generation • .gantt generation • Time used for .gantt generation

33. Memory constraint tab

34. Memory constraint tab • You can use Memory constraint tab to specify placement of variables in memory. • By default, the constant and non aging variables are respectively hardwired and stored in registers in the processing units. However, they can be placed in memory when the static attribute is used in the specification.

35. Results Viewer • Click on the pink box with the label of "Results viewer“ to generate GANTT chart of the synthesized circuit. • Click on the open icon and select "taylorexp_UT.gantt“ file. • GANTT chart shows the result of the scheduling step and also gives the information about the contents of the circuit in term of operators and registers.

36. GANTT chart Multiplier mul.2 performed operations mul_op0 [0-20)and mul_op2 [20-40) register.3 saved variables temp [10-50), temp000001 [50], ex [60]

37. GANTT chart • Horizontally, the blue color shows the execution of the operations and the orange color defines the variables and the registers in which they are stored. Vertically, the names of the operators and the registers are defined.

38. References • [1] GAUT user manual • [2] Philippe Coussy, et al, High-level synthesis from Algorithm to Digital Circuit, Springer, 2008.