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Focus 3: Cell. Sharon Sacco / MIT Lincoln Laboratory HPEC Workshop 19 September 2007.

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focus 3 cell

Focus 3: Cell

Sharon Sacco / MIT Lincoln Laboratory

HPEC Workshop

19 September 2007

This work is sponsored by the Department of the Air Force under Air Force contract FA8721-050C-0002. Opinions, interpretations, conclusions and recommendations are those of the author and not necessarily endorse by the United States Government.

embedded processor evolution
Embedded Processor Evolution

High Performance Embedded Processors

i860

SHARC

PowerPC

PowerPC with AltiVec

Cell (estimated)

  • 20 years of exponential growth in FLOPS / W
  • Requires switching architectures every ~5 years
  • Cell Processor is current high performance architecture

10000

GPU?

Cell

FPGA?

1000

MPC7447A

MPC7410

MPC7400

100

MFLOPS / W

SHARC

750

10

i860 XR

603e

1990

2000

2010

Year

cell features
Cell Features

Element Interconnect Bus

  • Synergistic Processing Element
  • 128 SIMD Registers, 128 bits wide
  • Dual issue instructions
  • 4 ring buses
  • Each ring 16 bytes wide
  • ½ processor speed
  • Max bandwidth 96 bytes / cycle (204.8 GB/s @ 3.2 GHz)
  • Local Store
  • 256 KB Flat memory
  • Memory Flow Controller
  • Built in DMA Engine

Cell offers significant performance benefits over other programmable technologies

(VMX)

  • Overall Performance
  • Peak FLOPS @ 3.2 GHz: 204.8 GFLOPS (single), 14.6 GFLOPS (double)
  • Processor to Memory bandwidth: 25.6 GB/s
  • Power usage: ~100 W (estimated)
  • Cell gives ~2 GFLOPS / W
in this session
In This Session
  • FFTC: Fastest Fourier Transform for the IBM Cell Broadband Engine
    • Virat Agarwal, Georgia Institute of Technology
  • Implementation of SIGINT Application on Cell-BE
    • Richard Besler, Black River Systems Company
  • Performance of a Multicore Matrix Multiplication Library
    • Robert Cooper, Mercury Computer Systems
other cell related talks
Other Cell Related Talks

Wednesday:

  • Session 4: Novel Applications
    • Projective Transform on Cell: A Case Study

Thursday:

  • Session 5: Multicore Environments
    • High Performance Simulations of Electrochemical Models on the Cell Broadband Engine
    • Sourcery VSIPL++ for the Cell/B.E.
    • Programming Examples that Expose Efficiency Issues for the Cell Broadband Engine Architecture
    • PVTOL: A High-Level Signal Processing Library for Multicore Processors
  • Focus 5: Benchmarking
    • Exploring Multi-core Processors with Realistic Signal- and Image-processing Application Benchmarks
  • Poster / Demo C: Cell / GPU Technologies
  • Session 6: Awards Session
    • Implementation of Polar Format SAT Image Formation on the Cell Broadband Engine