digital integrated circuits a design perspective n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Digital Integrated Circuits A Design Perspective PowerPoint Presentation
Download Presentation
Digital Integrated Circuits A Design Perspective

Loading in 2 Seconds...

play fullscreen
1 / 78

Digital Integrated Circuits A Design Perspective - PowerPoint PPT Presentation


  • 102 Views
  • Uploaded on

Digital Integrated Circuits A Design Perspective. Timing Issues. Timing Definitions. Latch Parameters. D. Q. Clk. T. Clk. PW m. t su. D. t hold. t d-q. t c-q. Q. Delays can be different for rising and falling data transitions. Register Parameters. D. Q. Clk. T. Clk. t hold.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Digital Integrated Circuits A Design Perspective' - perdy


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
latch parameters
Latch Parameters

D

Q

Clk

T

Clk

PWm

tsu

D

thold

td-q

tc-q

Q

Delays can be different for rising and falling data transitions

register parameters
Register Parameters

D

Q

Clk

T

Clk

thold

D

tsu

tc-q

Q

Delays can be different for rising and falling data transitions

clock uncertainties
Clock Uncertainties

Sources of clock uncertainty

clock non idealities
Clock Non-idealities
  • Clock skew
    • Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
  • Clock jitter
    • Temporal variations in consecutive edges of the clock signal; modulation + random noise
    • Cycle-to-cycle (short-term) tJS
    • Long term tJL
  • Variation of the pulse width
    • Important for level sensitive clocking
clock skew and jitter
Clock Skew and Jitter

Clk

  • Both skew and jitter affect the effective cycle time
  • Only skew affects the race margin

tSK

Clk

tJS

positive skew
Positive Skew

Launching edge arrives before the receiving edge

negative skew
Negative Skew

Receiving edge arrives before the launching edge

timing constraints
Timing Constraints

Minimum cycle time:

T -  = tc-q + tsu + tlogic

Worst case is when receiving edge arrives early (positive )

longest logic path in edge triggered systems
Longest Logic Path in Edge-Triggered Systems

TJI + d

TSU

Clk

TClk-Q

TLM

T

Latest point of launching

Earliest arrivalof next cycle

shortest path
Shortest Path

Earliest point of launching

Clk

TClk-Q

TLm

Clk

TH

Data must not arrivebefore this time

Nominalclock edge

clock distribution
Clock Distribution

H-tree

Clock is distributed in a tree-like fashion

the grid system
The Grid System
  • No rc-matching
  • Large power
self timed and asynchronous design
Self-timed and Asynchronous Design

Functions of clock in synchronous design

1) Acts as completion signal

2) Ensures the correct ordering of events

Truly asynchronous design

1) Completion is ensured by careful timing analysis

2) Ordering of events is implicit in logic

Self-timed design

1) Completion ensured by completion signal

2) Ordering imposed by handshaking protocol

hand shaking protocol
Hand-Shaking Protocol

Two Phase Handshake

2 phase handshake protocol
2-Phase Handshake Protocol

Advantage : FAST - minimal # of signaling events (important for global interconnect)

Disadvantage : edge - sensitive, has state

4 phase handshake protocol
4-Phase Handshake Protocol

Also known as RTZ

Slower, but unambiguous

4 phase handshake protocol1
4-Phase Handshake Protocol

Implementation using Muller-C elements

synchronizers and arbiters
Synchronizers and Arbiters
  • Arbiter: Circuit to decide which of 2 events occurred first
  • Synchronizer: Arbiter with clock f as one of the inputs
  • Problem: Circuit HAS to make a decision in limited time - which decision is not important
a simple synchronizer
A Simple Synchronizer

• Data sampled on rising edge of the clock

• Latch will eventually resolve the signal value,

but ... this might take infinite time!

phase detector
Phase Detector

Output before filtering

Transfercharacteristic

clock generation using dlls
Clock Generation using DLLs

Delay-Locked Loop (Delay Line Based)

fREF

U

PhaseDet

ChargePump

DL

D

Filter

fO

Phase-Locked Loop (VCO-Based)

fREF

U

PD

CP

VCO

D

÷N

Filter

fO

slide43

Building Blocks for Digital Architectures

Arithmetic unit

Bit-sliced datapath

(adder, multiplier, shifter, comparator, etc.)

-

Memory

- RAM, ROM, Buffers, Shift registers

Control

- Finite state machine (PLA, random logic.)

- Counters

Interconnect

- Switches

- Arbiters

- Bus

itanium integer datapath
Itanium Integer Datapath

Fetzer, Orton, ISSCC’02

the ripple carry adder
The Ripple-Carry Adder

Worst case delay linear with the number of bits

td = O(N)

tadder = (N-1)tcarry + tsum

Goal: Make the fastest possible carry path circuit

carry bypass adder
Carry-Bypass Adder

Also called Carry-Skip

carry bypass adder cont
Carry-Bypass Adder (cont.)

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

carry lookahead trees
Carry Lookahead Trees

Can continue building the tree hierarchically.

tree adders
Tree Adders

16-bit radix-2 Kogge-Stone tree

tree adders1
Tree Adders

16-bit radix-4 Kogge-Stone Tree

the barrel shifter
The Barrel Shifter

Area Dominated by Wiring

4x4 barrel shifter
4x4 barrel shifter

Widthbarrel ~ 2 pm M