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Figure 3.38. Compatibility of the IA-32 register structure with earlier Intel

Figure 3.38. Compatibility of the IA-32 register structure with earlier Intel processor register structures. Main. memory. address. doubleword. 1000. Base register EBP. 1000. *. *. *. *. 60 = displacement. *. *. Operand. 1060. Operand address (EA) = [EBP] + 60.

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Figure 3.38. Compatibility of the IA-32 register structure with earlier Intel

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  1. Figure 3.38. Compatibility of the IA-32 register structure with earlier Intel processor register structures.

  2. Main memory address doubleword 1000 Base register EBP 1000 * * * * 60 = displacement * * Operand 1060 Operand address (EA) = [EBP] + 60 (a) Base with displacement mode, expressed as [EBP + 60] 1000 Base register EBP 1000 40 * * Index register ESI * * * * 200 = displacement 1200 scale factor = 4 List of 4-byte * * ´ (double w ord) 160 = [Index register] 4 * * data items * * Operand 1360 * * * * * * * * * * * * ´ Operand address (EA) = [EBP] + [ESI] 4 + 200 (b) Base with displacement and index mode, expressed as [EBP + ESI * 4 + 200] Figure 3.39. Examples of addressing modes in the IA-32 architecture.

  3. LEA EBX,NUM1 Initialize base (EBX) and MO V ECX,N coun ter (ECX) registers. MO V EAX,0 Clear accum ulator (EAX) MO V EDI,0 and index (EDI) registers. * ST AR T ADD: ADD EAX,[EBX + EDI 4] Add next n um b er in to EAX. INC EDI Incremen t index register. DEC ECX Decremen t coun ter register. JG ST AR T ADD Branc h bac k if [ECX] > 0. MO V SUM,EAX Store sum in memory . (a) Straightforward approach LEA EBX,NUM1 Load base register EBX and – SUB EBX,4 adjust to hold NUM1 4. MO V ECX,N Initialize coun ter/index (ECX). MO V EAX,0 Clear the accum ulator (EAX). * ST AR T ADD: ADD EAX,[EBX + ECX 4] Add next n um b er in to EAX. LOOP ST AR T ADD Decremen t ECX and branc h bac k if [ECX] > 0. MO V SUM,EAX Store sum in memory . (b) More compact program Figure 3.40. IA-32 program for adding numbers.

  4. Calling program . . . LEA EBX,NUM1 Load parameters MO V ECX,N in to EBX,ECX. CALL LIST ADD Branc h to subroutine. MO V SUM,EAX Store sum in to memory . . . . Subroutine LIST ADD: PUSH EDI Sa v e EDI. MO V EDI,0 Use EDI as index register. MO V EAX,0 Use EAX as accum ulator register. * ST AR T ADD: ADD EAX, [EBX + EDI 4] Add next n um b er. INC EDI Incremen t index. DEC ECX Decremen t coun ter. JG STARTADD Branc h bac k if [ECX] > 0. POP EDI Restore EDI. RET Branc h bac k to Calling program. (a) Calling program and subroutine [EDI] ESP  Return Address Old TOS (b) Stack contents after saving EDI in subroutine Figure 3.45. Program of Figure 3.40a written as an IA-32 subroutine; parameters passed through registers.

  5. (Assume top of stac k is at lev el 1 b elo w.) Calling program PUSH OFFSET NUM1 Push parameters on to the stack. PUSH N CALL LIST ADD Branc h to the subroutine. ADD ESP ,4 Remo v e n from the stack. POP SUM P op the sum in to SUM. . . . Subroutine LIST ADD: PUSH EDI Sa v e EDI and use MO V EDI,0 as index register. PUSH EAX Sa v e EAX and use as MO V EAX,0 accummulator register. PUSH EBX Sa v e EBX and load MO V EBX,[ESP+20] address NUM1. PUSH ECX Sa v e ECX and MO V ECX,[ESP+20] load count n . * ST AR T ADD: ADD EAX,[EBX+EDI 4] Add next n umber. INC EDI Incremen t index. DEC ECX Decremen t coun ter. JG ST AR T ADD Branc h bac k if not done. MO V [ESP+24],EAX Ov erwrite NUM1 in stac k with sum. POP ECX Restore registers. POP EBX POP EAX POP EDI RET Return. (a) Calling program and subroutine  [ECX] Lev el 3 [EBX] [EAX] [EDI] Return Address  Lev el 2 n NUM1  Lev el 1 (b) Stack contents at different times Figure 3.46. Program of Figure 3.40a written as an IA-32 subroutine; parameters passed on the stack.

  6. Address Instructions Commen ts Calling program . . . 2000 PUSH P ARAM2 Place parameters 2006 PUSH P ARAM1 on stac k. 2012 CALL SUB1 2017 POP RESUL T Store result. ADD ESP ,4 Restore stac k lev el. . . . First subroutine 2100 SUB1: PUSH EBP Sa v e frame p oin ter register. MO V EBP ,ESP Load frame p oin ter. PUSH EAX Sa v e registers. PUSH EBX PUSH ECX PUSH ED X MO V EAX,[EBP+8] Get first parameter. MO V EBX,[EBP+12] Get second parameter. . . . PUSH P ARAM3 Place parameter on stac k. 2160 CALL SUB2 2165 POP ECX P op SUB2 result in to ECX. . . . MO V [EBP+8],ED X Place answ er on stac k. POP ED X Restore registers. POP ECX POP EBX POP EAX POP EBP Restore frame p oin ter register. RET Return to Main program. Second subroutine 3000 SUB2: PUSH EBP Sa v e frame p oin ter register. MO V EBP ,ESP Load frame p oin ter. PUSH EAX Sa v e registers. PUSH EBX MO V EAX,[EBP+8] Get parameter. . . . MO V [EBP+8],EBX Place SUB2 result on stac k. POP EBX Restore registers. POP EAX POP EBP Restore frame p oin ter register. RET Return to first subroutine. Figure 3.47. Nested subroutines in IA-32 assembly language.

  7. – – (j = n 1; j > 0; j = j 1) for – – { ( k = j 1; k > = 0; k = k 1 ) for { (LIST[ k ] > LIST[ j ]) if { TEMP = LIST[ k ]; LIST[ k ] = LIST[ j ]; LIST[ j ] = TEMP; } } } (a) C-language program for sorting LEA EAX,LIST Load list p oin ter base MO V EDI,N register (EAX), and initialize DEC EDI outer lo op index register – (EDI) to j = n 1. OUTER: MO V ECX,EDI Initialize inner lo op index – DEC ECX register (ECX) to k = j 1. MO V DL,[EAX + EDI] Load LIST(j) in to register DL. INNER: CMP [EAX + ECX],DL Compare LIST(k) to LIST(j).  JLE NEXT If LIST(k) LIST(j), go to next lo w er k index en try; X CHG [EAX + ECX],DL Otherwise, in terc hange LIST(k) and LIST(j), lea ving MO V [EAX + EDI],DL new LIST(j) in DL. NEXT: DEC ECX Decremen t inner lo op index k. JGE INNER Rep eat or terminate inner lo op. DEC EDI Decremen t outer lo op index j. JG OUTER Rep eat or terminate outer lo op. (b) IA-32 program implementation Figure 3.50. An IA-32 byte-sorting program using straight-selection sort.

  8. T ABLE 3.1 ARM index addressing modes Name Assembler syntax Addr essing function W ith immediate of fset: Pre-inde x ed [R n , #of fset] EA = [R n ] + of fset Pre-inde x ed with writeback [R n , #of fset]! EA = [R n ] + of fset;  R n [R n ] + of fset Post-inde x ed [R n ], #of fset EA = [R n ];  R n [R n ] + of fset W ith of fset magnitude in R m :   Pre-inde x ed [R n , R m , shift] EA = [R n ] [R m ] shifted Pre-inde x ed   with writeback [R n , R m , shift]! EA = [R n ] [R m ] shifted;   R n [R n ] [R m ] shifted  Post-inde x ed [R n ], R m , shift EA = [R n ];   R n [R n ] [R m ] shifted Relati v e Location EA = Location (Pre-inde x ed with = [PC] + of fset immediate of fset) EA = ef fecti v e address of fset = a signed number contained in the instruction shift = direction #inte ger where direction is LSL for left shift or LSR for right shift, and inte ger is a 5-bit unsigned number specifying the shift amount  R m = the of fset magnitude in re gister R m can be added to or subtracted from the contents of base re gister R n

  9. T able 3.2 68000 addressing modes syn tax Name Assem bler Addressing function Immediate #V alue Op erand = V alue Absolute Short V alue EA = Sign Extended WV alue Absolute Long V alue EA = V alue Register Rn EA = R n that is, Op erand = [R ] n Register Indirect (An) EA = [A ] n Autoincremen t (An)+ EA = [A ]; n Incremen t A n – Auto decremen t (An) Decremen t A ; n EA = [A ] n Indexed basic WV alue(An) EA = WV alue + [A ] n Indexed full BV alue(An,Rk.S) EA = BV alue + [A ] +[R ] n k Relativ e basic WV alue(PC) EA = WV alue + [PC] or Lab el Relativ e full BV alue(PC,Rk.S) EA = BV alue + [PC] + [R ] k or Lab el (Rk) EA = effectiv e address V alue = a n um b er giv en either explicitly or represen ted b y a lab el BV alue = an 8-bit V alue WV alue = a 16-bit V alue A = an address register n R = an address or a data register n S = a size indicator: W for sign-extended 16-bit w ord and L for 32-bit long w ord

  10. T able 3.3 IA-32 addressing modes Name Assem bler syn tax Addressing function Immediate V alue Op erand = V alue Direct Lo cation EA = Lo cation Register Reg EA = Reg that is, Op erand = [Reg] Register indirect [Reg] EA = [Reg] Base with [Reg + Disp] EA = [Reg] + Disp displacemen t  * Index with [Reg EA = [Reg] S + Disp S + Disp] displacemen t  * Base with index [Reg1 + Reg2 S] EA = [Reg1] + [Reg2] S  * Base with index [Reg1 + Reg2 S + Disp] EA = [Reg1] + [Reg2] S + Disp and displacemen t V alue = an 8- or 32-bit signed n um b er Lo cation = a 32-bit address Reg, Reg1, Reg2 = one of the general purp ose registers EAX, EBX, ECX, ED X, ESP , EBP , ESI, EDI, with the exception that ESP cannot be used as an index register Disp = an 8- or 32-bit signed n um b er, except that in the Index with displacemen t mode it can only b e 32 bits. S = a scale factor of 1, 2, 4, or 8

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