EE207: Digital Systems I, Semester I 2003/2004

1. EE207: Digital Systems I, Semester I 2003/2004 CHAPTER 4-ii: Sequential Circuits’ Analysis

2. Sequential Circuit Analysis • Standard Graphics Symbols • Characteristic Tables • Characteristic/Input Equations • State Tables • State Diagrams • Analysis using JK flip-flops Chapter 4-ii: Sequential Circuits (4.4)

3. S R SR-latch Standard Graphics Symbols Latches S D D R C C S’R’-latch D-latch with C=1 D-latch with C=0 Chapter 4-ii: Sequential Circuits (4.4)

4. Standard Graphics Symbols (cont.) Master-Slave Flip Flops J S J S C C C C K R K R Triggered JK Triggered SR Triggered JK Triggered SR Chapter 4-ii: Sequential Circuits (4.4)

5. Standard Graphics Symbols (cont.) Edge-triggered Flip Flops J D J D C C K C K C Triggered JK Triggered D Triggered JK Triggered D Rising Edge Falling Edge Rising Edge Falling Edge Chapter 4-ii: Sequential Circuits (4.4)

6. Characteristic Tables • Defines the logical properties of a flip-flop (such as a truth table does for a logic gate). • Q(t) – present state at time t • Q(t+1) – next state at time t+1 Chapter 4-ii: Sequential Circuits (4.4)

7. Characteristic Tables (cont.) Chapter 4-ii: Sequential Circuits (4.4)

8. Characteristic Tables (cont.) Chapter 4-ii: Sequential Circuits (4.4)

9. Characteristic Tables (cont.) Characteristic Equation: Q(t+1) = D(t) Chapter 4-ii: Sequential Circuits (4.4)

10. Characteristic Tables (cont.) Obtained by JK Flip-Flop with J=K=T Characteristic Equation: Q(t+1) = T’Q(t) + TQ(t)’ Chapter 4-ii: Sequential Circuits (4.4)

11. Asynchronous Set/Reset • Many times it is desirable to asynchronously (i.e., independent of the clock) set or reset FFs. • Example: At power-up so that we can start from a known state. • Asynchronous set == direct set == Preset • Asynchronous reset == direct reset == Clear Chapter 4-ii: Sequential Circuits (4.4)

12. S 1J C1 1K R Asynchronous Set/Reset (cont.) Cn indicates that Cn controls all other inputs whose label starts with n. In this case, C1 controls J1 and K1. Independent of CLK Independent of CLK Function Table IEEE standard graphics symbol for JK-FF with direct set & reset Chapter 4-ii: Sequential Circuits (4.4)

13. Sequential Circuit Analysis • Analysis: Consists of obtaining a suitable description that demonstrates the time sequence of inputs, outputs, and states. • Logic diagram: Boolean gates, flip-flops (of any kind), and appropriate interconnections. • The logic diagram is derived from any of the following: • Boolean Equations (FF-Inputs, Outputs) • State Table • State Diagram Chapter 4-ii: Sequential Circuits (4.4)

14. Flip-Flop Input Equations • An algebraic representation used to specify the logic driving the inputs of the FFs. • They imply the type of FFs to be used and fully specify the combinational logic that drives the FFs inputs. Chapter 4-ii: Sequential Circuits (4.4)

15. Example: Implementing FF Input Equations • Consider JA = XB+Y’C and KA = YB’+C • J, K imply the type of the FF (in this case, a JK-FF). • The index (A) denotes the output of the FF. Observe that the triggering type is not specified by the FF input eqs. You are either given this explicitly, or you have to assume it.For this case, we assume a positive edge-triggered clocking scheme. A JA J C A’ KA K Chapter 4-ii: Sequential Circuits (4.4)

16. Example: Implementing FF Input Equations X B JA A J Y C C KA A’ K Clock • JA = XB+Y’C • KA = YB’+C Chapter 4-ii: Sequential Circuits (4.4)

17. Fully specified logic diagrams • Do FF input equations fully specify a sequential circuit? No! • We also need the primary output boolean equations. List of boolean equationsfor the primary outputs. Comb. Circuit List of FF input equations. FFs Chapter 4-ii: Sequential Circuits (4.4)

18. Example • FF input equations: • DA = AX + BX • DB = A’X • Primary output boolean equations: • Y = (A + B)X’ •  # FFs: 2, FF-type: D •  # inputs: 1 (X), # outputs: 1 (Y) •  Logic diagram … (see Figure 4.18, pp. 203) Chapter 4-ii: Sequential Circuits (4.4)

19. State Table • Enumerates the relationship between inputs, outputs, and states of the sequential circuit. • Given a circuit with n inputs and m flip-flops, the corresponding state table contains 2n+m rows. Chapter 4-ii: Sequential Circuits (4.4)

20. State Table (cont.) DA = AX + BX = A(t+1) DB = A’X = B(t+1) Y = (A + B)X’ State Table Chapter 4-ii: Sequential Circuits (4.4)

21. State Table – Alternative Representation State Table Chapter 4-ii: Sequential Circuits (4.4)

22. Mealy Vs Moore machines • Mealy model: • Both outputs and next state depend both on primary inputs AND present state. • Moore model: • Only next state depends directly on primary inputs AND present state. Outputs depend only on present state. Chapter 4-ii: Sequential Circuits (4.4)

23. Canonical Sequential Circuit Combinational Network s(t+1) s(t) State Register next state present state x(t) present inputs clock output z(t) Chapter 4-ii: Sequential Circuits (4.4)

24. Mealy Machine C1 C2 s(t+1) State Register next state s(t) z(t) present state x(t) present inputs clock Chapter 4-ii: Sequential Circuits (4.4)

25. Moore Machine C2 C1 z(t) s(t+1) State Register next state s(t) present state x(t) present inputs clock Chapter 4-ii: Sequential Circuits (4.4)

26. X DA A D Z Y C clock Example of a Moore machine • Obtain the logic diagram and state table for: • DA = A  X Y • Z = A Chapter 4-ii: Sequential Circuits (4.4)

27. Example of a Moore machine (cont.) State Table Alternative State Table X DA A Z D Y C clock Chapter 4-ii: Sequential Circuits (4.4)

28. State Tables for JK flip-flops • Two step procedure: • Obtain binary values of each FF input equation in terms of present state and input variables. • Use corresponding FF characteristic table to determine the next state. Chapter 4-ii: Sequential Circuits (4.4)

29. Example • JA = B, KA = BX’ • JB = X’, KB = AX’ + A’X = A  X •  2 JK-FFs needed: JK-FF Characteristic Table JA JB J J B A C C KA A’ B’ KB K K Chapter 4-ii: Sequential Circuits (4.4)

30. Example (cont.) Step 1: Use FF input equations Chapter 4-ii: Sequential Circuits (4.4)

31. Example (cont.) Step 2:Use FF inputs and JK characteristic table Chapter 4-ii: Sequential Circuits (4.4)

32. State Diagrams • Graphical representation of a state table. • Graph node with label s denotes state s • Graph edge with label X denotes transition between two states when input X is applied S X Chapter 4-ii: Sequential Circuits (4.4)

33. Example: Mealy model State Table Possible states = { 00, 01, 10, 11 }  4 nodes in state diagram Chapter 4-ii: Sequential Circuits (4.4)

34. 0/0 1/0 01 00 0/1 0/1 0/1 1/0 10 1/0 11 1/0 Example: Mealy model (cont.) State Diagram I/O S1 S2 Reads as:When at state s1 and apply input I, we get output O and proceed to state s2. Chapter 4-ii: Sequential Circuits (4.4)

35. Example: Moore model State Table Possible states = { 0, 1 }  2 nodes in state diagram Chapter 4-ii: Sequential Circuits (4.4)

36. 00,11 01,10 0/0 1/1 01,10 00,11 Example: Moore model (cont.) State Diagram I S1/O1 S2/O2 Reads as:When at state s1 with output O1 and apply input I, we proceed to state s2 with Output O2. Chapter 4-ii: Sequential Circuits (4.4)