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Pipelined ADC

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Pipelined ADC

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    1. – 1 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Pipelined ADC

    2. – 2 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009

    3. – 3 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 A 1.5-Bit Stage 2X gain + 3-level DAC + subtraction all integrated Digital redundancy relaxes the tolerance on CMP/RA offsets

    4. – 4 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Timing Diagram of Pipelining Two-phase nonoverlapping clock is typically used, with the coarse ADCs operating within the nonoverlapping times All pipelined stages operate simultaneously, increasing throughput at the cost of latency (what is the latency of pipeline? 1 T?)

    5. – 5 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 1.5-Bit Decoding Scheme

    6. – 6 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 A 2.5-Bit Stage

    7. – 7 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 2.5-Bit RA Transfer Curve 6 comparators + 7-level DAC are required Max tolerance on comparator offset is ±VR/8

    8. – 8 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 2.5-Bit Decoding Scheme

    9. – 9 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Pipelined ADC Features Architecture complexity is proportional to the resolution N = Snj Throughput is significantly improved relative to algorithmic or SAR Digital redundancy works the same way as algorithmic Inter-stage gain enables stage scaling to save power and area Limitations Typically 3 conversion operations are involved Sample-and-hold Sub-ADC comparison Sub-DAC and residue generation High-gain op-amps are required to produce residue signals with certain accuracy, which limits the conversion speed Long latency may be problematic for certain applications

    10. – 10 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 No Stage Scaling

    11. – 11 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Aggressive Stage Scaling

    12. – 12 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Optimum Stage Scaling

    13. – 13 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 References

    14. – 14 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 References

    15. – 15 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Subranging ADC

    16. – 16 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Subranging ADC Architecture

    17. – 17 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Subranging ADC Features Reduced complexity – 2·(2N/2-1) comparators – relative to flash Reduced Cin, area, and power consumption No residue amplifier required (compare to pipelined ADC) Limitations Typically 3 clock phases per conversion Sample Coarse comparison Fine comparison Typically two SHAs are required for the coarse and fine ADCs Fine comparator offset must be controlled to N-bit level Offset tolerance on coarse comparators can be relaxed with digital redundancy

    18. – 18 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Typical Subranging Block Diagram

    19. – 19 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Digital Redundancy in Fine ADC

    20. – 20 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Two-Step Subranging/Pipelined ADC Coarse-fine two-step subranging architecture Conversion residue produced instead of switching reference taps Residue gain can be provided to relax offset tolerance in fine ADC Very similar to the pipelined architecture

    21. – 21 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 Timing Diagram Four conversion steps can be pipelined (needs op-amp) Usually DAC + RA settling consumes most of the conversion time Residue gain of unity is often used to speed up conversion

    22. – 22 – Advanced Analog IC Design Pipelined & Subranging ADCs Professor Y. Chiu ECE 581 Fall 2009 References

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