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Reconfigurable Computing Part II . Roadmap of Presentation . Static and Dynamic Configurable Systems Piperench: A Reconfigurable Architecture and Compiler. Static & Dynamic Reconfiguration . Static: Configuration string is loaded once and does not change until the end of the task

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reconfigurable computing part ii

Reconfigurable Computing Part II

Reconfigurable Computing

roadmap of presentation

Roadmap of Presentation

Static and Dynamic Configurable Systems

Piperench: A Reconfigurable Architecture and Compiler

Reconfigurable Computing

static dynamic reconfiguration

Static & Dynamic Reconfiguration

Static: Configuration string is loaded once and does not change until the end of the task

Dynamic: Configuration can change at any point

Reconfigurable Computing

objectives of static configuration

Objectives of Static Configuration

Improvement of Performance

Optimizing the utilization of resources (gates & power consumption....)

Reconfigurable Computing

an application of static configuration spyder

An Application of Static Configuration: SPYDER

A reconfigurable co-processor adaptable to given application in a transparent way

The application is written with a high level language, compiler generates the best description for the hardware

Reconfigurable Computing

system description of spyder

System Description of SPYDER

Reconfiguration takes place in processing unit composed of 3 FPGAs connected to two register banks

Each FPGA has independent access to registers for parallel processing

FPGA size & # registers are limitations for configuration!

Reconfigurable Computing

user configuration

User Configuration

First aim was transparent HW configuration

The user just determines the operators in a high level language

Compiler then generates the corresponding code and does operations based on maximal parallelism.

Reconfigurable Computing

spyder architecture

SPYDER Architecture

Reconfigurable Computing



Performance of SPYDER surpasses that of classical architectures.

SPYDER @8MHz computes the future states of 115M cells, while SPARC @85MHz can do 6.5M states.(skeletonization, edge detection)

Reconfigurable Computing

another static configuration application renco

Another Static Configuration Application: RENCO

A reconfigurable network computer for improved performance of the system

RENCO adds the power of reconfiguration to the network computer.

User can download not only his/her application but also the processor configuration

Reconfigurable Computing



Composed of two parts:

1. A conventional network computer with a processor: Motorola MC68EN360

RENCO’s µ-processor has high communication capabilities, integrated memory controller, and many SW tools are available.

2. A reconfigurable part: A cluster of FPGAs connected to their own memories and processor buses

Reconfigurable Computing



Reconfigrable part contains 4 Altera Flex FPGAs. Each has up to 1M logic gates

Processor bus is connected to 4 FPGAs so that they can act as co-processors and each FPGA memories can be accessed by the processor.

14 layer PCB!

Reconfigurable Computing

renco block diagram

RENCO Block Diagram

Reconfigurable Computing



Network computer requires a good OS for networking

For reconfigurable part many SW tools are availale(synthesizer, monitor for resource access & configuration loading, debugger etc)

Java(Kaffe) is used for source code. HW libraries are built accordingly

So like other reconfigurable systems SW is much harder than HW!

Reconfigurable Computing



Since HW libraries are currently unavailable cannot make proper evaluation for performance

However the idea of downloadable HW architecture is amazing.

Also this idea can be used as prototype for complex logic design

Reconfigurable Computing

objective of dynamic configuration

Objective of DYNAMIC Configuration

To handle changing and/or incomplete specifications

Reconfigurable Computing

an application of dynamic configuration firefly

An Application of Dynamic Configuration: FIREFLY

Based on the idea of applying the biological principle of natural evolution to artificial systems

A genetic algorithm is iterative procedure that starts with a random initial population

Reconfigurable Computing

general description

General Description

Aim is to reach the “best individuals” by evolutionary steps in which the individuals are evaluated according to some predefined quality criterion

In order to create next generation, individuals are subjected to genetic operators(cross-over, mutation, etc...) This iteration with these operations results in the best generation

Firefly machine implements this algorithm in a reconfigurable manner

Reconfigurable Computing



Firefly is based on cellular automata model consisting of an array of cells whose states are updated in every evolutionary step.

A rule table, concerning the neighbour’s state, exists for the determination of the next state

After some steps iteration leads the cells to oscillate between all 0’s and all 1’s.

Firefly inherits its name from this phenomenon

Reconfigurable Computing



Firefly has 56 cells consisting of FPGA’s as the evolution platform.

Firefly is a machine in which all the system evolution is carried out online, that is in hardware!

Evolution rules and state of a cell are stored in D-flipflops.

Reconfigurable Computing

firefly board

FireFly Board

Reconfigurable Computing

performance and future

Performance and Future

All operation are carried our in HW with no external reference

High performance workstation execute 60 configurations while Firefly can execute 13000 configurations per second

Evolving machines(like Firefly) operating in autonomous manner can be used in the field of autonomous robots and of controllers for noisy and changing environments.

Reconfigurable Computing

another application of dynamic reconfiguration biowatch

Another Application of Dynamic Reconfiguration: BIOWATCH

Objective is to development of VLSICs capable of self repair and self replication

Biowatch is an artificial organism deigned to count seconds & minutes thus a modulo-3600 counter.

Multicellular organism each cell realizing a unique function described by the gene of the cell.

Reconfigurable Computing



Dynamic reconfiguration of the executing task occurs during the self-repair process

The cells interprets the the genome(whole set of genes)

The cell executes the operations According to the relevant part of the genomes(genes) which configures it

Reconfigurable Computing



Coarse grained FPGAs are used. Each cell holds a 4-bit state register. 4 four-bit buses enter the cells from the neigbour cells.

4 output buses also go to neighbours

Binary decision machine of the cell executes µ-programs(genomes) written using a set of 6 instructions

Each cell is implemented in a Actel 1020 FPGA circuit

Reconfigurable Computing

self repair

Self Repair

Self repair of artificial organism allows partial reconstruction of the original device in case of a minor fault

Faulty Cell is by-passed and all or a part original cellular array is shifted to the right

New Coordinates lead to dynamic configuration of the executing task of cell

Reconfigurable Computing

self repair1

Self Repair

Reconfigurable Computing

self replication
Self Replication
  • Self repair of an artificial organism allows for the complete reconstruction of the original device in case of a major fault

Reconfigurable Computing

pipelined reconfiguration
Pipelined Reconfiguration
  • Piperench, a new reconfigurable fabric, combines the flexibility of conventional procesors with the efficiency of custom HW to achieve extreme performance speed-up
  • Piperench is a reconfigurable fabric consisting of an interconnected network of configurable logic and storage elements.
  • Pipelined reconfiguration implements a large logical configuration on a small piece of HW through rapid reconfiguration of that HW

Reconfigurable Computing

general procedure
General Procedure
  • Pipelined reconfiguration involves virtualizing pipelined computations by breaking a single static configuration into pieces
  • Each piece of configuration corresponds to pipeline stages in the application
  • Physically 3 but functionally 5 stages!

Reconfigurable Computing

virtualization process
Virtualization Process
  • Stage1 configured in cycle 1, and executes for two cycles.
  • There is no physical pipe stage 4, therefore in cycle 4 the fourth virtual pipe stage is configured in physical stage 1

Reconfigurable Computing

virtualization process1
Virtualization Process

Reconfigurable Computing

virtualization process2
Virtualization Process
  • Reconfiguration does not decrease performance since some stages are configured while others are executed
  • Configuration takes 1 cycle in successfull applications since wide on-chip configuration buffer and a small controller are employed

Reconfigurable Computing

stripe pipeline stage
Stripe(Pipeline Stage)

Reconfigurable Computing

stripe architecture
Stripe Architecture
  • Piperench contains a set of physical pipeline stages called stripes
  • Each PE contains ALU each of which contain LUTs

Reconfigurable Computing

benefits of piperench
Benefits of Piperench
  • Improved Compilation Time
  • Improved Reconfiguration Time

Reconfigurable Computing

  • “Static and Dynamic Configurable Systems”
  • “Piperench: A Reconigurable Architecture and Compiler”
  • “Reconfigurable Conputer Architectures and Design Methods”

Reconfigurable Computing