instructor nachiket m kharalkar lecture 17 date 07 16 2007 e mail knachike@ece utexas edu l.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Instructor: Nachiket M. Kharalkar Lecture 17 Date: 07/16/2007 E-mail: knachike@ece.utexas.edu PowerPoint Presentation
Download Presentation
Instructor: Nachiket M. Kharalkar Lecture 17 Date: 07/16/2007 E-mail: knachike@ece.utexas.edu

Loading in 2 Seconds...

play fullscreen
1 / 43

Instructor: Nachiket M. Kharalkar Lecture 17 Date: 07/16/2007 E-mail: knachike@ece.utexas.edu - PowerPoint PPT Presentation


  • 447 Views
  • Uploaded on

Introduction to Microcontrollers Instructor: Nachiket M. Kharalkar Lecture 17 Date: 07/16/2007 E-mail: knachike@ece.utexas.edu Today’s Agenda Output compare interrupt DAC Lab 6 discussion Multiple Access Circular Queues First in first out queue Implementation of OC

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Instructor: Nachiket M. Kharalkar Lecture 17 Date: 07/16/2007 E-mail: knachike@ece.utexas.edu' - paul


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
instructor nachiket m kharalkar lecture 17 date 07 16 2007 e mail knachike@ece utexas edu

Introduction to Microcontrollers

Instructor: Nachiket M. Kharalkar

Lecture 17

Date: 07/16/2007

E-mail: knachike@ece.utexas.edu

today s agenda
Today’s Agenda
  • Output compare interrupt
  • DAC
  • Lab 6 discussion
  • Multiple Access Circular Queues
  • First in first out queue

Nachiket M. Kharalkar

implementation of oc
Implementation of OC

Nachiket M. Kharalkar

typical oc handler
Typical OC handler

;interrupts every 1000 TCNT cycles

;every 1ms

TC0handler

lddTC0

addd #1000

stdTC0;setp time for next interrupt

movb #$01,TFLG1;acknowledge, clear C0F

rti

Nachiket M. Kharalkar

resistor network for dac
Resistor network for DAC

1.5 kΩ

1.5 kΩ + 1.5 kΩ

12 kΩ || 12 kΩ

12 kΩ

Nachiket M. Kharalkar

dynamic testing
Dynamic testing

Nachiket M. Kharalkar

4 bit sine table
4-bit sine table

SinTab fcb 8,9,11,12,13,14,14,15,15,15,14

fcb 14,13,12,11,9,8,7,5,4,3,2

fcb 2,1,1,1,2,2,3,4,5,7

Nachiket M. Kharalkar

440hz sine wave output
440Hz sine wave output

Nachiket M. Kharalkar

data flow graph
Data flow graph

Nachiket M. Kharalkar

lab 6 demo
Lab 6 demo

Nachiket M. Kharalkar

standard music notes
Standard music notes

Nachiket M. Kharalkar

extra credit
Extra credit
  • At least 2 output compare interrupts
  • Play a song
  • Worth +20 maximum for this lab

Nachiket M. Kharalkar

lab 6 extra credit demo
Lab 6 Extra credit demo

Nachiket M. Kharalkar

multiple access circular queues
Multiple Access Circular Queues
  • Used for data flow problems source to sink
  • Digital filters and digital controllers
  • Fixed length
  • Order preserving
  • MACQ is always full

Nachiket M. Kharalkar

slide15
Source process (producer)
    • places information into the MACQ
    • oldest data is discarded when new data isentered
  • Sink process (consumer)
    • can read any data
    • MACQ is not changed by the read operation.

Nachiket M. Kharalkar

perform a 60hz notch filter on a measured signal
Perform a 60Hz notch filter on a measured signal
  • v[0] v[1] v[2] and v[3] are the most recent data sampled at 360 Hz.
  • filtered output =

Nachiket M. Kharalkar

60hz filter implementation
60Hz filter implementation

Nachiket M. Kharalkar

first in first out queue and double buffers
First in first out queue and double buffers

FIFO queues and double buffers can be used to pass data from a producer to a consumer

Nachiket M. Kharalkar

producer consumer examples
Producer-consumer examples

Nachiket M. Kharalkar

a data flow graph showing two fifo s that buffer data between producers and consumers
A data flow graph showing two FIFO’s that buffer data between producers and consumers

Nachiket M. Kharalkar

program 11 1 code fragments showing the basic idea of a fifo
Program 11.1. Code fragments showing the basic idea of a FIFO

* Reg A is data to put into the FIFO

RxFifo_Put

ldx RxPutPt

staa 1,X+ store into FIFO

stx RxPutPt update pointer

rts

* Reg A returned with byte from FIFO

RxFifo_Get

ldx RxGetPt

ldaa 1,X+ read from FIFO

stx RxGetPt update

rts

Nachiket M. Kharalkar

three modifications that are required to these functions
Three modifications that are required to these functions
  • If FIFO full when RxFifo_Put is called then the subroutine should return a full error.
  • If the FIFO is empty when RxFifo_Get is called, then the subroutine should return an empty error.
  • A finite number of bytes will be permanently allocated

Nachiket M. Kharalkar

slide27
RXFIFO_SIZE equ 10

RxPutPt rmb 2

RxGetPt rmb 2

RxFifo rmb RXFIFO_SIZE

Program 11.2. Global structures for a two-pointer FIFO.

RxFifo_Init ldx #RxFifo

stx RxPutPt

stx RxGetPt

rts

Program 11.3. Initialize both pointers to the beginning of the FIFO.

Nachiket M. Kharalkar

serial communications interface sci
Serial Communications Interface ( SCI)
  • The total number of bits transmitted per second is called the baud rate.
  • M, selects 8-bit (M=0) or 9-bit (M=1) data frames.
  • A frame is the smallest complete unit of serial transmission.
  • The information rate, or bandwidth, is defined as the amount of data or usual information transmitted per second.

A serial data frame with M=0

Nachiket M. Kharalkar

6812 sci details
6812 SCI Details

9S12C32 SCI ports.

Nachiket M. Kharalkar

scibd scidrl
SCIBD & SCIDRL
  • SCIBD
    • on 9S12C32 MCLK = 24MHz (with PLL)

= 4 MHz (otherwise)

    • SCI baud rate = __MCLK__

(16*BR)

    • TE is the Transmitter Enable bit, and
    • RE is the Receiver Enable bit.
  • SCIDRL register contains transmit and receive data
    • these two registers exist at the same I/O port address
    • Reads access the read-only receive data register (RDR)
    • Writes access the write-only transmit data register (TDR)

Nachiket M. Kharalkar

tdre rdrf
TDRE & RDRF
  • TDRE is the Transmit Data Register Empty flag.
    • set by the SCI hardware if transmit data register empty
    • if set, the software write next output to SCIDRL
    • cleared by two-step software sequence
      • first reading SCISR1 with TDRE set
      • then SCIDRL write
  • RDRF is the Receive Data Register Full flag.
    • set by hardware if a received character is ready to be read
    • if set, the software read next into from SCIDRL
    • cleared by two-step software sequence
      • first reading SCISR1 with RDRF set
      • then SCIDRL read

Nachiket M. Kharalkar

transmitting in asynchronous mode
Transmitting in asynchronous mode

Data and shift registers implement the serial transmission.

  • The software writes to SCIDRL, then
  • 8 bits of data are moved to the shift register
  • start and stop bits are added
  • shifts in 10 bits of data one at a time on TxD line
  • shift one bit per bit time (=1/baudRate)

Nachiket M. Kharalkar

receiving in asynchronous mode
Receiving in asynchronous mode

Data register shift registers implement the receive serial interface

  • The receiver waits for the 1 to 0 edge signifying a start bit, then
  • shifts in 10 bits of data one at a time from RxD line
  • shift one bit per bit time (=1/baudRate)
  • start and stop bits are removed
  • checked for noise and framing errors
  • 8 bits of data are loaded into the SCIDRL

Nachiket M. Kharalkar

three receive data frames result in an overrun or error
Three receive data frames result in an overrun (OR) error
  • If there is already data in the SCDR when the shift register is finished, it will wait until the previous frame is read by the software, before it is transferred.
  • An overrun occurs when there is one receive frame in the SCDR, one receive frame in the receive shift register, and a third frame comes into RxD.

Nachiket M. Kharalkar

slide36
A device driver is a collection of software functions that allow higher level software to utilize an I/O device.
    • Collection of public methods (subroutines)
      • SCI_Init
      • SCI_InChar
      • SCI_OutChar
    • Collection of private objects (subroutines, globals, I/O ports)
      • SCICR2
      • SCIBD
      • SCISR1
      • SCIDRL
  • Complexity abstraction
    • divide a complex problem into simple subcomponents
  • Functional abstraction
    • divide a problem into modules
    • grouped by function

Nachiket M. Kharalkar

sci i o programming
SCI I/O Programming

; Initalize 9S12C32 SCI at 250000 bps

; Inputs: none

; Outputs: none

; Errors: none

; assumes 4MHz E clock (PLL not activated)

SCI_Init

movb #$0c,SCICR2 ;enable SCI TE=RE=1

movw #1,SCIBD ;250000 bps

;baud rate (bps) = 250000/BR

rts

Nachiket M. Kharalkar

sci inchar
SCI_InChar

Busy‑waiting, gadfly, or polling are three equivalent namessoftware continuously checks the hardware status waiting for it to be ready

Nachiket M. Kharalkar

sci outchar
SCI_OutChar

Nachiket M. Kharalkar

ascii strings
ASCII strings
  • Stored with null-termination
  • In C, the compiler automatically adds the zero at the end
  • In assembly, the zero must be explicitly defined

Msg fcc “EE319K is fun”

fcb 0

Msg2 fcb “EE319K is fun”,0

Nachiket M. Kharalkar

strings arrays
Strings & Arrays
  • A string is a data structure
    • with equal size elements
    • only allows sequential access
    • always read in order from the first to the last.
  • An array is a data structure
    • with equal size elements
    • allows random access to any element in any order

Nachiket M. Kharalkar

sci demo
SCI Demo

Nachiket M. Kharalkar