1 / 21

Analysis and Avoidance of Cross-talk in on-chip buses

This paper discusses the analysis and avoidance of cross-talk in on-chip buses, including the classification of cross-talk types and methods for eliminating 3C and 4C sequences. Experimental results are presented to validate the proposed solutions.

Download Presentation

Analysis and Avoidance of Cross-talk in on-chip buses

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Analysis and Avoidance of Cross-talk in on-chip buses Chunjie Duan Ericsson Wireless Communications Anup Tirumala Jasmine Networks Sunil P Khatri University of Colorado, Boulder

  2. Outline • Introduction • Classification of Cross-talk types • Eliminating 3C and 4C sequences • Eliminating 4C sequences • Experimental Results • Conclusions

  3. v a a CI CI v CL CL CL a CI CI w a v a CI CI v a a CI CI v a a CI CI v CL CL CL CI CI v v CL CL CL CL CL CL a CL CL CL a CL CL CL a s t Introduction • Deep sub-micron process • Verified cross-talk trends • Accurate 3-D capacitance extraction • Delay variation 2.47:1 (200 mm wires, 10X drivers, 0.1 mm technology)

  4. Cross-talk vs Bus Data Pattern • When λ ~ 0.1μm, r = CI/CL > 10 (metal 4) • Effective total capacitance depends on bus data sequence : • Best case: 0 x CI x L • Worst case: 4 x CI x L 0·CI 0·CI 2·CI 2·CI Ctotal = 4 ·CI Ctotal = 0 ·CI

  5. Classification of Cross-talk • 4·C sequence: • 3·C sequence • 2·C sequence • 1·C sequence • 0·C sequence • Forbidden patterns (“010” and “101”)

  6. Eliminating 3C & 4C Sequences • Motivation • Maximum bus data rate depends on total capacitance seen by any bit • Removing 3C and 4C sequences will increase the maximum data rate • Simple approach: shielding • g s g s g s g... (ground line between signals) • No 3C or 4C sequences possible • However, bus-width is doubled • Coding gain = (throughput/area)with coding (throughput/area)without coding • Coding gain = 0 for this approach - 1

  7. Eliminating 3C & 4C Sequences • Theorem: If no forbidden patterns are allowed on the bus, • Proof: see paper • Our approach: • Encode the data on the bus to get rid of the forbidden patterns • Questions to be answered: • What is the number of redundancy bits (and the coding gain)? • How to practically implement such a CODEC ?

  8. Number of Redundancy Bits • Map the n bit bus to a k=n+r bit bus so that • the k bit data bus has no forbidden patterns • Definitions: • T(n): number of distinct n-bit vectors. • T(n)=2n • TB(n): number of n-bit vectors which contain a forbidden pattern • TG(n): number of n-bit vectors which do not contain forbidden patterns • Let the sets of vectors be V(n), VB(n), and VG(n) respectively • Let v(n), vB(n) and vG(n) respectively represent an element of these sets • TGG(n): Number of n-bit vectors in VG(n) with last 2 bits ‘00’ or ‘11’ • TGB(n): number of n-bit vectors in VG(n) with last two bits ‘01’ or ‘10’ • Goal: to find the smallest k such that

  9. Counting Forbidden Vectors • v(n) can be constructed by appending {0,1} to any v(n-1) • Two v(n) are constructed from any v(n-1) • Two vB(n) are constructed from any vB(n-1) • xxx010xx -> xxx010xx0, xxx010xx1 • One vGG(n) and one vGB(n) are constructed from any vGG(n-1) • xxxxxx00 -> xxxxxx000, xxxxxx001 • One vGG(n) and one vB(n) are constructed from any vGB(n-1) • xxxxxx01 -> xxxxxx010, xxxxxx011

  10. Counting Forbidden Vectors • Algorithm • Initial conditions (n=3) • T(3) = 8, TG(3) = 6, TB(3)=2, TGG(3)=4, TGB(3)=2 • Inductive step • T(n) = 2 x T(n-1); • TG(n) = 2 x TG(n-1) + TG(n-1) • TGG(n) = TGG(n-1) + TGB(n-1) • TB(n) = 2 x TB(n-1) + TGB(n-1)

  11. Eliminating 3C & 4C sequences • 44% overhead when n > 30 bits • Coding gain

  12. 3C & 4C CODEC Implementation • Implements a one-to-one map from V(n) to VG(k) • Look-Up Table, straightforward, can achieve minimum overhead (44%), but not practical • Our implementation • 62.5% overhead (higher than minimum) • Modular and straightforward • Break bus into 4-bit groups • Encode each group independently (4bit -> 5 bit) • Additional logic to handle across-the-boundary forbidden patterns • Ripple effect (Eliminated by pipelining)

  13. b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 3C & 4C CODEC Implementation CODEC block diagram

  14. Eliminating 4C sequences • Less aggressive: eliminating 4C sequences only • Less overhead(33%) : simpler implementation • Simpler algorithm • Divide the bus into 3 bit groups • When 4C sequence occurs, complement group data • Insert group complement indicator • Special handling for across-the-boundary forbidden sequences (see paper for details) • Examples: • 101 001 -> 010 010 • 1010 0010 -> 1011 0100

  15. Experimental Results • Bus simulations • CODEC was not modeled • Spice3, 0.1μm model • Transmission line with inter-wire coupling • Quantify delay dependency on bus vector sequences • CODEC implementation • Currently implemented 3C & 4C CODEC • Matching delay on CODEC outputs • 4C CODEC implementation planned in future

  16. Bus Simulation Results • Bus length 5mm, 10mm or 20mm • Driver strength 30X, 60X and 120X of minimum

  17. Recovered sequence Recovered sequence Random sequence Random sequence encoder encoder decoder decoder driver driver receiver receiver CODEC Results • Compare waveform with coding and w/o coding • Random input sequence • Encoder/decoder delay ~250ps • Max data rate more than 2X compared to scheme with no encoding

  18. CODEC Results • random sequence directly into bus buffer • 20mm trace • 45x buffer • > 1ns delay variation • Random sequence into 3C & 4C encoder • 20mm trace • 45x buffer • < 500ps delay variation

  19. Experimental Results Reshaped data after receivers • without coding, • edge jitter ~ 1000ps • with coding • edge jitter < 500ps

  20. Conclusions • Inter-wire capacitance increasingly significant in DSM VLSI interconnect • Total capacitance is heavily dependent on bus data sequence • With 44% overhead, we can eliminate 3C & 4C cross-talk • Compared to shielding, which has 100% overhead • Implemented CODEC to eliminate 3C and 4C cross-talk sequences • Proposed CODEC to eliminate 4C cross-talk sequences with 33% overhead • Simulation results match our analysis.

  21. Thank You!

More Related